The design of analog elements is not yet as automated as for digital circuits. EDA tools nevertheless support the design process. An overview of the analog or full-custom design
Appendix A Introduction to ASIC design Development of a DCS Chip Test bench RTL Code Simulation Synthesis FPGA /ASIC Place and route
Post-Synthesis Simulation
Library
Netlist and design Post-PnR Simulation
Figure A.7: Schematic representation of digital design flow.
Figure A.8: Logic block of the PSPPv3 as an example of a generated digital design. The power rails go around the logic and there are vertical rails to provide power for logic cells.
Appendix A Introduction to ASIC design
Schematic design
Design Rule Check (DRC) Layout Schematic Simulation (Corners, MC ...) Design Kit Layout vs. Schematic Check (LVS) Parasitic Extraction Post-Layout simulation Integration
Figure A.9: Schematic representation of analog design flow.
flow is given in Figure A.9. Design kits contain information from the foundry like device models for simulation, physical properties for layout and the design rules.
Each analog design starts with a schematic as shown in Figure A.10 on the next page. The schematic defines connections between transistors and other elements, like resistors or capacitors. An analog circuit is normally split into small parts to simplify the design and to reuse circuits like amplifiers.
Simulations are an essential part of analog design. Once the function of a circuit is defined, transistors and other elements have to be properly sized i.e. the physical dimensions to be defined. This is required to guarantee that the circuit operates as intended in all expected conditions.
Characteristics of elements depend on temperature, process variations and also radi- ation (see sections 3.1 and 3.2). These variations are different for each technology and therefore it is not straightforward to transfer a design from one technology to another. Process variations are measured by the foundry and implemented in design models. They are grouped in different corners to represent extreme cases. A corner simulation is per- formed to verify that a circuit works across the desired temperature range within all design corners. Figure A.11 on page 157 shows an example of such a simulation. It can be seen that the output voltage varies depending on the corner. Furthermore, a Monte Carlo simulation is run to analyze a randomized set of process variations. This gives fur-
Appendix A Introduction to ASIC design Development of a DCS Chip
Figure A.10: Schematic of a comparator circuit as an example for an analog design. ther insight into the expected yield and how design parameters can change the operating point of a circuit.
Once the circuit performs as desired in simulation, it has to be drawn as a layout. Analog layouts are drawn manually to have full control. This is important to guarantee that transistors are matching. All transistors in a current mirror or from a differential pair should have the same orientation and same surroundings. This is used to assure that transistors observe the same process variations during fabrication. A better matching improves the performance of the circuit and can increase the yield. Used techniques for matching are interleaving transistors for a symmetric arrangement or adding of dummy transistors for a common surrounding. Figure A.12 on page 158 shows an example layout of a differential pair where both techniques were applied. More details on transistor matching are given for example in [37].
A layout is based on layers, which are used to create masks for production. See section A.4 for more details on how an ASIC is fabricated. The layout has to follow design rules, which are checked by a dedicated tool. It is usually referred to as design rule check (DRC). Another software tool is used to verify that layout and schematic represent the same circuit. The layout vs. schematic (LVS) tool extracts designed devices and interconnection from the layout. The extracted circuit is compared to its schematic and the tool verifies that both are equivalent, including size and parameters of devices.
Parasitic elements appear in the circuit due to the tracks. For example, each metal line is a small resistor and two parallel lines form a parasitic capacitor. The extraction of parasitics is done after finishing the layout of a circuit. Analog simulations are repeated, taking parasitic information into account, to ensure that a design is still fulfilling all requirements.
Once all elements are designed, they can be integrated into the top-level design. For digital-top, it is necessary to create a file containing all information for the PnR tool.
Appendix A Introduction to ASIC design
Different BG voltages depending on corner
Figure A.11: Simulation of a bandgap (BG) with different corners. An analog block cannot be connected correctly without this information.
For the analog-top approach, it is good practice to start with IO pads. Pads are connections to external signals. Creating a padframe in an early stage of the design process is helpful to reduce problems with design rules, which are different if pads are included. The blocks are integrated one by one into the padframe and DRC and LVS are performed after each new block is added. This method was used for the development of the PSPP and proved to be very efficient.