C on tact system s and patterns.

N-type ohmic contacts comprised a 500Â NiAuGe eutectic layer, capped by a 1000Â of Au. The Au-Ge system possesses a eutectic temperature of 356°C [18]. Above this temperature a liquid melt forms at the metal-GaAs boundary and GaAs dissolves into this. Upon cooling GaAs epitaxially regrows from the melt, incorporating a high concentration of Ge in the regrown material. This generates the n^ layer, forming the tunnelling contact [16,18]. Nickel is added to the eutectic to improves it’s ‘wetting’ capacity to GaAs. P-type ohmic contacts were composed of a multilayer system; 100Â Au:150A Zn:1000A Au. The first Au layer allowed the alloy to ‘wet’ to the GaAs surface, whilst zinc doped the p^ layer to the required hole density.

N-type contacts were made to flat (100) surfaces on the patterned (100) substrates and (100) facets on the patterned (110) substrates. P-type contacts were made to the converse surfaces. Due to the small physical size of the facets (-10pm ) the contact was run onto the facet from the flat surface, to allow sufficient area for probing. Where the contact overlays semiconductor material of differing conductivity type, a p-n junction was formed. Upon application of bias, the formed junction became reverse biased. Due to diode action, this prevented current injection into everywhere except the ohmic contact on the facet. The different contact systems for both upper and lower lateral p-n junctions on the (100) and (110) GaAs patterned substrates are shown in Figure 3.9. n-type metallisation Upper junction n-type metallisation p-type metallisation current flow (1 0 0 ) Patterned G aA s Substrate p-type metallisation current flow (110) Patterned

G aA s Substrate _junctionLower

Figure 3.9. Metallisation scheme for the (100) and (110) pattered substrates.

Extending the contact from the lower flat surface onto the facet allowed the upper junction to be characterised, whilst the converse enabled the lower junction to be profiled.

3.7

Capacitance-Voltage Profiling.

A p-n junction is formed when two pieces of semiconductor with opposite conductivités are brought into contact. Diffusion of carriers occurs due to the concentration gradients between materials. Once across the junction these carriers recombine, exposing impurity ions [19]. Diffusion currents therefore flow between the differing materials. On the p-side of the junction negative acceptor ions are uncovered, whilst positive donor ions are evident on the n-side. Space charge regions are created on either side of the junction and an electric field is established, directed from positive to negative. The field opposes further carrier diffusion and limits the spread of the space charge regions [19]. Within the space charge regions carrier densities are very low and they are therefore termed depletion regions. However, minority electrons in the p-type material or holes in the n-type material are accelerated by the electric field and drift across the junction, forming drift currents. These are in the oppose sense to the diffusion currents and at thermal equilibrium the currents balance and no net current flows across the junction [19]. A fuller discussion of p-n junction theory is presented in Chapter 6.

The space charge distribution and electrostatic potential \|/ within a semiconductor are given by Poisson’s equation;

(3.23) Ç Ç = ^ ^ = . ± { N ^ - + p . n)

d x d x gg gg

where E is the electric field, ps the space charge density, &s the semiconductor dielectric permittivity, Na,d are the ionised impurity concentrations and p and n

the hole and electron densities [19]. Within the depletion region p = n = 0. Therefore equation (3.23) reduces to;

(3.24) n-side:- ^ ^ p-side:- ^ ^

dx gg d x gg

junction to be precisely equal:

(3.25) Na^p =

and the total depletion width:

(3.26) W = X p + Xn

where Xn,p are the n- and p-side depletion widths [19]. Solution of Possions equation for both sides of the depletion region using the above set of equations yields an expression for W for an abrupt junction;

(3.27) 1/1/ =

q

where Va is the applied bias and Vbi the built-in voltage. A similar expression can be developed for linearly graded junctions, with W (Vbi±VA)^^^ (equation(6.16)).

Application of a negative voltage to the n-type material (positive to the p- type) causes electrons (holes) to be injected into the depletion region, partially compensating the ionised donors (acceptors) and reducing the depletion width. Similarly, reversing the voltage direction causes an increase in the depletion region width, as charge is removed from the region boundaries [19]. These voltage conditions are termed forward and reverse bias, respectively. When reverse bias is applied to the junction the depletion region expands, increasing the charge stored within its boundaries. This situation is analogous to a parallel- plate capacitor, with the depletion width acting as the separation between the charge plates [19]. The capacitance is termed the depletion capacitance.

The depletion capacitance per unit area C is given by C = dO / dV, where dQ

is the change in depletion layer charge with voltage increment dV [19]. From Possions equation, the change in stored charge causes an increase in the depletion field dQ = d E /es and d \f can be approximated by dV=W dE=W {dO/es).

Therefore;

^ " W " " w

which is the equation for a parallel-plate capacitor [20]. Substituting equation (3.27) into (3.28) yields a C-V expression for abrupt junctions;

(3.29) C = ^A

Na + A/^