Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<31:24> 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<15:8> 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0 (1) CiFIFOBA<7:0> Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits
Defines the base address of all message buffers. Individual message buffers are located based on the size of the previous message buffers. This address is a physical address. Note that bits <1:0> are read-only and read ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
DS61154C-page 34-42 © 2009-2012 Microchip Technology Inc.
31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSIZE<4:0>(1)
15:8 U-0 S/HC-0 S/HC-0 R/W-0 U-0 U-0 U-0 U-0
— FRESET UINC DONLY(1) — — — —
7:0 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0>
Legend: S = Settable bit HC = Hardware clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’ bit 20-16 FSIZE<4:0>: FIFO Size bits(1)
11111 = FIFO is 32 messages deep •
• •
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep bit 15 Unimplemented: Read as ‘0’ bit 14 FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should poll if this bit is clear before taking any action
0 = No effect
bit 13 UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message bit 12 DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier bit 11-8 Unimplemented: Read as ‘0’
bit 7 TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-43
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34
bit 6 TXABAT: Message Aborted bit(2)
1 = Message was aborted
0 = Message completed successfully bit 5 TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent
0 = Message did not loose arbitration while being sent bit 4 TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO) Setting this bit to ‘1’ requests sending a message.
The bit will automatically clear when all the messages queued in the FIFO are successfully sent Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a Receive FIFO) This bit has no effect.
bit 2 RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXPR<1:0>: Message Transmit Priority bits
11 = Highest Message Priority
10 = High Intermediate Message Priority
01 = Low Intermediate Message Priority
00 = Lowest Message Priority
Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
DS61154C-page 34-44 © 2009-2012 Microchip Technology Inc.
31:24 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE 23:16 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE 15:8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — TXNFULLIF(1) TXHALFIF TXEMPTYIF(1)
7:0 U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0
— — — — RXOVFLIF RXFULLIF(1) RXHALFIF(1) RXNEMPTYIF(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty bit 23-20 Unimplemented: Read as ‘0’
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty bit 15-11 Unimplemented: Read as ‘0’
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a Receive Buffer) Unused, reads ‘0’
© 2009-2012 Microchip Technology Inc. DS61154C-page 34-45
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bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is ≤ half full
0 = FIFO is > half full
TXEN = 0: (FIFO configured as a Receive Buffer) Unused, reads ‘0’
bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
bit 7-4 Unimplemented: Read as ‘0’
bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit TXEN = 1: (FIFO configured as a Transmit Buffer) Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer) Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer) Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is ≥ half full
0 = FIFO is < half full
bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
DS61154C-page 34-46 © 2009-2012 Microchip Technology Inc. 31:24 R-x R-x R-x CiFIFOUAn<31:24>R-x R-x R-x R-x R-x 23:16 R-x R-x R-x CiFIFOUAn<23:16>R-x R-x R-x R-x R-x 15:8 R-x R-x R-x CiFIFOUAn<15:8>R-x R-x R-x R-x R-x 7:0 R-x R-x R-x R-x R-x R-x R-0 (2) R-0(2) CiFIFOUAn<7:0> Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown