The benefit of a geometric program formulation is that it can be solved in polyno- mial time using for example interior point methods. The first posynomial formula- tion for transistor/gate sizing was introduced by Fishburn and Dunlop [FD85] and formed the basis for subsequent formulations of the gate sizing problem as geomet- ric program. Recall from Section 3 that in order to get a geometric program, the objective function and the inequality constraints need to be formulated as posyn- omials. The objective function is of the form cost(x) = Pn
i=1αiξi, which already
is a posynomial. Edge delays can be expressed as posynomials by modeling gates and nets as RC-circuits under the Elmore delay model.
4.4.1 Posynomial Delay Models
We model wires and gates likewise as RC-circuits and use the Elmore delay model to compute the actual delays following Shyu et al. [Shy+88] and Chen, Chu and Wong [CCW99]. Figure 4.2 shows a 2-input gate gi ∈ G and its representation by
4.4 Convex Program for the Continuous Relaxation
capgi
capgi
resgi
Figure 4.2: An AND gate and its switch-level RC circuit model: It contains a ca- pacitance element capgi for each input pin, and an output resistor resgi.
two capacitors (one for each input pin) and one resistor. To simplify notation, all input pin capacitances are assumed to be equal. Let ξi be the size of gi. We have
resgi := res]gi/ξgi, and
capgi := capggi · ξgi+ ˜fgi
for the resistance resgi and the capacitance capgi of gi, where ]resgi,gcapgi and ˜fgi
are gate type specific constants denoting the unit size output resistance, the unit size gate capacitance and the gate perimeter capacitance of gi, respectively. Wire
segments are modeled by a resistor enclosed by two capacitors. We assume wire resistances and capacitances (i.e. wire lengths) to be constant because the impact of gate sizing on wire lengths is marginal. Consequently, load capacitances only depend on the sizes of the gates in the design, and the same holds for the delay and slew functions for all edges in the timing graph if we assume input slews at timing start points to be constant.
Recall from Section 2.5.3 that for each e = (v, w) ∈ E there is a delay function for each transition and each signal traversing e. For simplicity of notation we assume from now on that the delay for rising and falling transitions do not differ, and that there exists only one phase, i.e. we do not distinguish between signals originating
from different timing start points. For e ∈ E let delaye0(ξ), ξ ∈ Ξ
delaye0 : Ξ → R≥0 (4.4)
be the delay function for e that only depends on the gate sizes.
Now let e = (v, w) ∈ E and let N ∈ N be the output net of gate g with wire capacitance wirecap(N ). If e is an edge traversing gate g, we have
delay0e(ξ) := resgg ξg X g0∈succ(g) g capg0ξg0+ wirecap(N ) + X w0∈V end∩succ(w) pincap(w0) , (4.5)
where ξ is the vector of gate sizes and pincap(w0) is constant for w0 ∈ Vend. Other- wise, if e is a wire edge, its delay is the Elmore delay (2.25) from Section 2.5.6 and can also be expressed as a function depending on the gate sizes:
delay0e(ξ) := X e0=(p,q)∈S[v,w] rese0 cape0 2 + loadq(ξ) , (4.6)
where loadq(ξ) is the capacitance of all wire segments in the Steiner tree S realizing
N plus the capacitances of all sink pins of N that are reachable from q. The sink pin capacitances depend linearly on the sizes of the sink gate or, if they are timing output pins, are constant.
In reality the delay through a gate edge is a concave function of the load capaci- tance for constant input slew, and not linear as in (4.5). Furthermore, slews are not considered in this model which tags it as rather inaccurate. Several variants with higher accuracy have been proposed that incorporate for example slews, intrinsic circuit capacitances, rising and falling signal transitions etc. We refer to the tu- torial on geometric program-based gate sizing by Boyd et al. [Boy+05] for a more comprehensive overview and references.
4.4.2 Simplifying the Timing Constraints
Recall that the timing constraints require that for each path P in the timing graph, the signal needs to arrive on time at its endpoint p, i.e.
atq+
X
e∈P
delay0e(ξ) ≤ ratp
for all paths P in G with required arrival time ratpat its endpoint, and arrival time
atq at its start point. This formulation is impractical as the number of paths in G
depends exponentially on the number of vertices in G. However, the constraints can be partitioned into constraints on delay across the edges by introducing for each v ∈ V an arrival time variable av ∈ R for the signal arrival time. For v ∈ Vstart Arrival time vari-
able av we fix a
v := atv and for v ∈ Vend we fix av = ratv, where atv and ratv are the
prescribed signal arrival times and required arrival times, respectively. This leads to the following formulation of the timing constraints:
av+ delaye0(ξ) ≤ aw ∀ e = (v, w) ∈ E. (4.7)
Remark 4.1 Note that this simplification is independent of the delay model, and also holds for discrete size variables. Transition times and more than one phase can be considered by introducing multiple constraints for each edge.
4.4 Convex Program for the Continuous Relaxation
4.4.3 The Geometric and the Convex Program
With the posynomial delay approximations and the simplified timing constraints we arrive at the geometric program formulation of the continuous relaxation:
Geometric Program for the gate sizing problem min cost(ξ)
subject to av+ delaye0(ξ) ≤ aw ∀ e = (v, w) ∈ E
ξ ∈ Ξ
(4.8)
We transform the geometric program into a convex program by variable transfor-
mation xi = log(ξi) for all i = 1, . . . , n (cf. Section 3.1). Let Xcont
Xcont:= {x ∈ Rn: li:= log(ιi) ≤ xi ≤ ui := log(µi), i = 1, . . . , n}, (4.9)
denote the set of feasible sizes after variable transformation, and Ic:= [lc, uc] ⊂ R. Ic= [lc, uc]
We denote the resulting convex delay functions with delaye(x) for x ∈ Xcont, and delaye(x)
formulate the convex program:
Convex program for the gate sizing problem
min cost(x) := n X i=1 αiexi subject to av+ delaye(x) ≤ aw ∀ e = (v, w) ∈ E x ∈ Xcont (4.10) cost(x)
In the remainder of this thesis we will assume that the objective function and all delay functions are convex functions of load capacitance and input slew and do not elaborate on the underlying posynomial delay model.
Recall that we have a bijection between Bgi and the set X
i
disc for each gi ∈ G.
To simplify notation in the following chapters, we assume Xdisc ⊂ Xcont and
size(gi) = exi holds for xi ∈ Xdisci . We denote the cost induced by size xi with
cost(xi) := αiexi. cost(xi)
Remark 4.2 (Additional constraints) Note that other constraints are also compat- ible with the geometric program formulation, for example constraints on maximum load capacitances of primary input pins, or slew. We refer to Section 6.6 and the tutorial of Boyd et al. [Boy+05] for an overview.