Chapter 3 Device Modelling
3.3 Developments in Large-Signal Device Modelling
Self-heating and trapping induced dispersion influences the GaN HEMT performance, and therefore these effects have to be incorporated into a large-signal model in order to accurately represent a real GaN device in simulation.
Self-heating arises from the power dissipation in GaN HEMT devices. The power dissipation (Pdiss) can be calculated from (3.4):
58
W P
W P
W P
WPdiss DC in out (3.4)
Here, Pin, Pout and PDC are the input, output and consumed DC power respectively. Typically, GaN HEMT based RF PAs are biased at high drain voltage and high current. The power dissipation in the GaN device at these bias conditions is high, and consequently the internal temperature of the device rises during operation. The DC power consumption increases even further as a function of RF input signal at the gate. Due to the power dissipation, the channel temperature can reach several hundred degrees above the ambient temperature. The phonon scattering in the crystal is increased because of this increased temperature and as a result, the electron mobility (µ) is decreased. Therefore, as displayed in Figure 3.4, the drain current decreases at high power level and results in a negative differential output conductance.
0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
I
DS(
A
)
V
DS(V)
Cree CGH40025 (25 W GaN-on-SiC) VGS= -4 V to 1.5 V, Step = 0.5 V Decrease in IDS due to self-heatingFigure 3.4: Measured I-V characteristic of Cree CGH40025, a 25 W GaN-on-SiC HEMT with self- heating effect. The drain current (IDS) decreases at high power level and results in a negative differential
output conductance
It can be observed that this effect is not so strong at low drain voltages. Sometimes, this can also be represented with the nonlinear characteristics of source (Rs) and drain (Rd) resistances with increasing temperature. These effects are known as the self- heating effects in GaN HEMTs and significantly influences the device IDS-VDS characteristic and performance. Severe self-heating reduces device lifetime and can even cause device failures which greatly affect overall reliability.
Chapter 3
59
The RF output power measured at microwave frequencies for GaN HEMTs has been reported to be lower than the expected value based on the DC I-V characteristics. This degradation of the device performance can be attributed to reduction in drain current and an increase in the knee voltage. This occurrence has been termed as the “knee walkout”, “current collapse”, “current slump” or “DC-to-RF” dispersion. This behaviour is related to the existence of two kinds of traps in device structure: surface traps and buffer or substrate traps.
In surface trapping, electrons, as shown in Figure 3.5, are confined into the surface states in the AlGaN barrier layer of the AlGaN/GaN devices. These electrons act like a negatively biased metal gate that gives rise to the concept of ‘virtual gate’ [3.71] which depletes the 2DEG of electrons and thus increases the parasitic resistances of the devices.
Figure 3.5: Locations of surface and buffer traps.
The traps in the buffer or substrate are generally the result of impurities or defects in the crystalline. Electrons get trapped into these energy states due to hot-electron injection at high drain voltage. These trapped electrons cannot take part in the conduction and as a result, the drain current is reduced. When a RF input signal is applied to a device, it changes the gate and drain voltages. Since the capture time is very short compared to the relatively long emission time of the electrons from the traps, for a RF signal at microwave frequency, the drain current cannot keep up with the change in gate and drain voltages. Hence, these mechanisms are also called “gate- lag” and “drain-lag”. The current collapse and gate-lag due to the surface states can be minimized by appropriate surface passivation such as silicon nitride, although the exact mechanism of this is not clearly know yet. It has been suggested that passivation
60
stabilizes the charge at the surface and the interface [3.72], increases the positive charge at the Si3N4/AlGaN interface [3.73], modifies donor states at the surface [3.71] or reduces the surface trap density [3.74]. Implementation of a field-plate in the device structure lessens the electric field at the drain edge of the gate which reduces the hot- electron injection into the buffer layer [3.75] and this can reduce the drain-lag. Most of the recent large-signal models such as in [3.27], [3.76] - [3.86] use either analytical functions, temperature-dependent parameters or sub-circuits to include the trapping and self-heating effects.
Using frequency and temperature dependent parameters in the expressions, Angelov et al. extended [3.64] the Chalmers model to include the temperature effects and frequency dispersion. The temperature dependency of main parameters is obtained by extracting the values in the temperature range of 17- 400 K and the frequency dispersion are taken into account by additional parameters whose values are obtained from DC and pulsed I-V and S-parameter measurements. Angelov et al. expressed the drain current as:
V t V t
I
V
t V
t
I
V
t V
t
I
V
t V
t
Ids,RF gs , ds ds,DC gs , ds ds gs , ds ds gs , ds (3.5)The second and third terms on the right-hand side of (3.5) incorporates the dispersion effects into the drain current with frequency dependent parameters in the expressions for ΔI and ds ΔIds.
The temperature effects are implemented to the model using linear function:
T R A TRs s0 Rs (3.6)
Here, the function Rs(T) represents the temperature dependency of the source resistance Rs, where Rs0 is the value at room temperature, ARs is the linear temperature coefficient and ΔT is the difference between temperatures.
The second approach to incorporate self-heating and trapping induced dispersion in the equivalent circuit models is introducing sub-circuits. Curtice et al. extended [3.87] the Curtice model to include the gate-lag, drain-lag and self-heating effects by adding sub-circuits for each phenomenon as shown in Figure 3.6.
Chapter 3
61
Figure 3.6: Curtice et al. [3.87] added sub-circuits in the FET model to incorporate the gate-lag, drain-lags and temperature effects.
The gate-lag and drain-lag circuits in the model in Figure 3.6 sample the gate and drain voltages and feed fractions of these voltages back to the gate. These feedback factors and the time constant of the RC circuit are the lag parameters. The thermal sub-circuit consists the device thermal resistance (Rth) and thermal capacitance (Cth). The values of the parameters can be extracted from measurements [3.80] or physics-based simulation [3.86]. In [3.78], a transistor in series with the main transistor has been used as the virtual gate to account the DC-to-RF dispersion. In [3.79], the sub-circuits add transients to gate voltage based on the capture and emission time of the charges from the traps. In the other models, a four-terminal circuit topology is used to characterize the trapping dispersion. In this approach, the current is described as a function of DC and RF gate and drain voltages as in (3.7):
DSq DC GSq DC dsRF gsRF
DS f V V v v
I , , , , , , , (3.7)
The static and dynamic components are separated by RC filter networks at gate and drain terminals.
Most of these models also include the nonlinear characteristics of other parameters such as Cgs and Cgd which are extracted from pulsed S-parameter measurement at multi-bias points.
62