The electronic set up was quite straight forward and involved five separate systems:
1. SLM Control - A USB cable was connected to the Multi-driver controller which, in turn, was connected by 4 ribbon cables which sent data in parallel to the SLM. (The SLM controller was initially mounted on the instrument rack as its cooling fan made it too noisy to be position on the optical bench. Even so the mechanical action of the SLM introduce enough noise to have an effect below 10Hz, see below.)
2. AOM Control - Each AOM was driven by a signal from an Agilent 33250A signal generator which was passed through a PA-4 RF power amplifier with a minimum gain of 40dB.
3. Fast Steering Mirror Control - The FSM was driven by its controller which in turn was driven by a signal from a third Agilent signal generator.
4. LabVIEW ADCs - signals from segments of the photodiodes and the sync pulse from the SLM controller were passed to a LabVIEW junction box which in turn passed them to the FPGA (8channels, 16 bit resolution and a 40MHz clock rate enclosed in a National Instruments USB-7856R LabVIEW chassis).
5. System Clock - the LabVIEW chassis used did not have a clock input so a 10MHz clock was developed in LabVIEW, passed out through a digital channel and then daisy-chained to synchronise the other equipment. The digital channel was power with a 5V power supply.
This information is summarised below in figure 5.3
During operation it became clear that there was some cross talk between these systems, particularly the leads from the three photodiodes to the LabVIEW control box. photodi- odes were disconnected while not in use to minimise this feedback.
5.4 Electronic Set Up
~
1. SLM Control Matlab SLM Controller SLM 2. AOM Control~
Power Amp Sig Gen AOM 3. FSM Control FSM Controller FSM Sig Gen 4. LabVIEW ADCs LabVIEW FPGA LabVIEW ADC Sync Pulse 5. 10 MHz Clock LabVIEW FPGA LabVIEW DAC Signal Gens Matlab ControllerFigure 5.3: A schematic showing the 5 control systems used in the first experiment.
The Spatial Light Modulator
The spatial light modulator was the centrepiece of the experiment. It was a segmen- ted spatial light modulator (specifically a Boston Micromachines Multi-DM 1.5µm) and comprised a 12 by 12 array of gold coated mirrors each of which could be advanced in- dependently by up to 1.5 microns. (The mirror’s in the corners were fixed in the 0% or flat position making the actual number of active elements 140.) It is a micro electromech- anical systems (MEMS) device, packaged and wire bonded to a ceramic chip carrier and sealed in a window enclosure which has a slightly angled face to help deflect unwanted reflections away from the optic line. The sealed chip carrier is integrated into a compact aluminium enclosure which can be mounted in most standard 2-inch optical mounts (See Section 2.2.3 and Ref [97]) Elements were controlled by creating an array of 140, 14-bit numbers in Matlab and sending them to the SLM controller (see below) which converted them to voltages and passed them in parallel to the SLM where they initiated a change of state. Numbers in the array were percentages with 0% leaving an actuator in the flat po- sition, 100% generating the full 1.5 µm and values in between generating a proportionate response. The controller recognised 14-bit numbers suggesting a minimum actuator step of 1.5µm/16384 or 0.0916nm. (The technical specifications guarantee only movement of less than 1nm but even this was more than adequate for the experiments reported here because of the low dependency on modulation depth.) The attributes of the SLM used in this experiment are shown in Table 5.4.
The SLM Controllers
Each SLM is managed by a controller, figure 5.5 and Ref [97], which has the job of converting the array of numbers created by Matlab or LabVIEW into the voltages which drive the actuators and passing them to the SLM through a parallel cable. Each SLM is matched individually to its controller by a driver which, besides facilitating data transfer
Chapter 5 Wavefront Sensing and Correction
Figure 5.4: The performance specifications of the Segmented SLM.
also adjusts the output voltages to match the specific characteristics of the SLM so that it performs within the tolerances promised. Drivers, SLM and controllers must be used as a matched set for accurate performance. The calibration for the SLM used in this experiment is provided at Ref [98].
Controllers can be either Multi Drivers or X-Drivers. The Multi Driver is linked to the controlling PC using a USB connection. It is cheaper but introduces a degree of un- certainty about the arrival times of new arrays because the USB channel competes with other resources, being managed by the operating system (Windows 10), and executes with non-deterministic timing. In practical terms, this limited operational frequencies to approximately 2 kHz. X-Drivers are connected to the PC through a PCIe bus and are supposed to be able operate at up to 400 kHz although we have been unable to test this because, as yet, no suitable drivers are available, see Ref [99]. Given that the errors on modern PC clocks are of the order of 11 PPM, see Ref [100], and the PC driving the SLM controller used a 2.7 GHz clock, the effect of PC clock jitter on the X-Driver would be minimal. As always budget was a consideration and so a Multi-driver was used in the proof of concept and the timing uncertainties had to be managed (see Section 5.4.1).
Determining the Sampling Window
The SLM is a mechanical device and, when it is connected through a Multi-driver to a host PC, especially when it is running other software (typically, the LabVIEW Host and the Matlab mirror controller), its operating frequency is variable. It can run reliably at around 2kHz but this remains a variable operating frequency. The heterodyne frequency of the beat note between the two AOMs was selected at 160kHz and, consequently, there were around 80 cycles of the heterodyne frequency for each code change. (The examples in Chapter 3 were based on multiple code changes per heterodyne cycle but either arrange- ment works equally well.)
5.4 Electronic Set Up
Figure 5.5: The Segmented SLM USB Controller.
A new mirror shape was initiated as soon as the controller received a new array. Samples could only be taken when the system had settled into a stable state, that was after the SLM had changed shape and settled, and before the USB interface sent the next array. This proved more difficult than first thought.
The complications were threefold:
1. Accurately determining the true finish of the sync pulse. 2. Accommodating a settling time for the mirror.
3. Managing the uncertainty around the USB interface and the arrival time of the next sync pulse.
Every time the SLM changed state it sent a synchronisation pulse (sync pulse) to the LabVIEW ADC. The sync pulse manifested as a voltage increase on a signal line, which rose from 0V to 3.3 volts for 31µs. The mirror had now transitioned to a new state. Experiment showed that this was followed by a settling time of up to 40 micro-seconds which depended on the magnitude of the actuator movement. Large movements oscillated for longer before they settled. Once the settling time had finished a window opened which allowed the collection of reliable data (that is, data not corrupted by transients in the actuators) and this continued until the controller provided the voltages to initiate the next change. This, of course, was also somewhat unpredictable so the data collection challenge was to identify a suitable data collection window after the SLM had changed state and settled and before a new transition started.
A typical cycle was as follows and allowed for reliable sampling for 75% of the total cycle time:
Chapter 5 Wavefront Sensing and Correction
2. Settle Time - mirror settled into new configuration - up to 40µs depending on the degree of actuator movement.
3. Sample Time - period of time during which reliable data could be collected.
4. Safety Buffer - safety margin which allowed for the shortest, likely time before a new sync pulse is received. (The occasional sample which overlaps the start of arrival of the next USB pulse is tolerable but it cannot be allowed to extend pass the end of the next sync pulse or the codes will get out of sync.)
V ol ta ge (V ) 0 3.3 Time (μs)
1st Sync Pulse Settle Time Sample Time Safety Buffer 2nd Sync Pulse
USB Variability over 4 Cycles Settling Variability
Figure 5.6: A typical SLM cycle showing how the variability of the settling time, and arrival of the next sync pulse reduce the safe sampling time to about 75% of the total cycling.
This is illustrated in figure 5.6 and summarised in table in figure 5.7. Ticks refers to FPGA cycles which occurred at 40MHz, so 1µs was 40 ticks. It was vitally important to keep track of all of these changes because, as figure 3.4 shows, the demodulation only works if the code used to demodulate remains in phase with the code used to do the initial tagging.
Stage
μs
Ticks
% of Total
Sync Pulse
31
1240
1.55%
Settle Time
219
8760
10.95%
Sample Time
1500
60,000
75.00%
Safety Buffer
250
10000
12.50%
Total
2000
80,000
100.00%
Figure 5.7: Typical sampling windows available for reliable data collection during the cycling of the SLM. The reliable sampling time was 75% of the total cycle. Ticks refers to LabVIEW cycles which ran at 40mHz. 1µs is 40 ticks.
The settle time and minimum time between sync pulses were determined by observation and rechecked regularly during data collection using an oscilloscope. Determining that a