Energy Reduction Efficiency (Static Slack)

In this subsection, the proposed HSASC and HSAMC algorithms are com-pared with existing approaches in terms of energy reduction efficiency in the absence of dynamic slack, i.e., all the tasks run until their WCETs. Before the evaluation results are presented, a set of relevant reference algorithms are first explained.

In the context of the RTSC problem, 3 algorithms from existing studies are selected for comparison:

• NoDVS: There is no DVS strategy at all. All the tasks run at the highest speed. This algorithm is in fact a DPM preferred version, because all the tasks are finished as soon as possible. There is more idle time for the DPM usage. Note that the solution computed by this strategy is also used as the initial solution for the HSASC algorithm.

• PureDVS: This is the counterpart of NoDVS, where all the tasks are ex-ecuted at the lowest possible speed. This algorithm is a DVS preferred version. Since running all the tasks at the lowest speed may violate hard real-time constraints, i.e., the lowest speed may not always ensure system schedulability, hereby a solution described in Proposition 1 in [Ayd+04] is adopted. In brief, they computed a constant speed S for all the tasks within a continuous range of speeds, i.e., they have assumed an ideal DVS model. This work, however, focuses on a more realistic

model, which provides a finite number of discrete operating frequen-cies. Thus, their solution is adapted by selecting the next available speed above S.

• CSDVS: This is a critical speed oriented DVS strategy, where all the tasks are executed at the respective critical speed. There is a similar problem here as for PureDVS, because the critical speed is computed without taking into consideration system feasibility. Therefore, the speed assignment scheme from [JG04] is adopted in this case. Ba-sically, all the tasks are initially assigned with their critical speeds.

Afterward, a heuristic is developed to incrementally and iteratively in-crease the assigned speeds until system schedulability is ensured. More specifically, in each iteration all the tasks are investigated and one task will be selected, so that its assigned speed is increased by one level, i.e., to the next higher speed. Concerning task selection, the one resulting in minimal energy increase is selected.

Figure 8.1 shows the simulation results on the Intel XScale processor plat-form comparing the HSASC algorithm with the other algorithms in terms of energy reduction efficiency. Hereby HSAx indicates the HSASC algorithm with the termination parameter β = x, e.g., HSA0.01 has the termination pa-rameter β = 0.01. Moreover, the shown results are classified in terms of num-ber of tasks in a task set, which is indicated by the x-axis. In addition, the y-axis shows solution values, i.e., system energy consumption, by applying different algorithms. Note that hereby all the solution values are normalized with regard to the value obtained by NoDVS.

By looking at the HSASC algorithm, it is obvious that the smaller the β, the better result the HSASC algorithm can achieve. As expected, HSA0.01 saves more energy than HSA0.05 and HSA0.1. Furthermore, this experiment shows that HSA0.01 algorithm outperforms all the other reference algorithms in all cases. More interestingly, the energy reduction efficiency of the HSASC algorithm remains at the same level, as the number of tasks increases. This obviously indicates that the HSASC algorithm scales well in terms of input size.

Similar results can be observed for ARM based platforms as well, which are shown in Figure 8.2.

In the context of RTMC, the LA+LTF+FF algorithm from [CHK06] is chosen as a reference. LA+LTF+FF is a two stage static approach where in the first stage it tries to perform a balanced task partition and in the second stage some tasks are reallocated, so that some processor cores could become idle and therefore may be completely shut down at run-time. More concretely, the first stage adopts the worst fit and largest task first strategy, i.e., the tasks are sorted in a non-increasing order of their utilization at the beginning. The

0,8

NoDVS PureDVS CSDVS HSA0.1 HSA0.05 HSA0.01

Figure 8.2: Energy reduction efficiency comparison among different algo-rithms in terms of task number (ARM Cortex-A8 processor based platform)

algorithm then partitions a task, in the task order, to the processor core with the smallest utilization among all the cores, i.e., the most lightly loaded core.

After the task partition, for each processor core there will be a frequency selected and then assigned to all the tasks on the core. This frequency is chosen as low as possible, however above the respective critical speed. In the second stage, the set of processor cores with relatively lower utilization are considered, i.e., the cores with the utilization lower than a defined threshold.

The main idea is to ”reshuffle” the tasks on such processor cores, so that some cores may become completely idle. Hereby the first fit strategy is adopted for task reallocation. As has been proven by the authors, the LA+LTF+FF algorithm is in fact an 1.667-approximation algorithm for per-core platforms, provided that the processor cores may operate at any frequency within a given range.

According to Chapter 4, the HSAMC algorithm starts with an initial solution generated by partitioning tasks using the worst fit strategy. In this evaluation, however, the algorithm adopts the solution of the LA+LTF+FF algorithm as the starting point. The main reason is due to extremely large solution space of the RTMC problem and starting with a ”good” solution will significantly improve the search performance.

Figures 8.3 and 8.4 show the simulation results on the (I2)²and I2A2 plat-forms. Hereby the algorithms are denoted in a similar way as for single-core processor platforms, e.g., HSAMC0.01 denotes the HSAMC algorithm with β = 0.01. In the figures, the x-axis shows the number of tasks and the y-axis gives the power consumption of output solution normalized to the solution of the LA+LTF+FF algorithm. Clearly, HSAMC0.01 achieved the best results in all the cases and the smaller the β, the more power saving can be obtained.

The similar observation can be found as well according to further

simula-0,8 0,85 0,9 0,95 1 1,05

7 8 9 10 11 12 13 14

normalized power consumption

size of task sets

LALTFFF HSAMC0.1 HSAMC0.05 HSAMC0.01

Figure 8.3: Energy reduction efficiency comparison among different algo-rithms in terms of task number ((I2)²)

tion results on the I2, (I1)², I4 and (I1)⁴platforms, which are provided in Appendix A.1.