This section summarizes previous methods, which can be used to analyse the detection of a given small delay fault by a given set of test vector-pairs under the impact of delay variations.
The statistical timing analysis of large circuits can be drastically simplified by neglecting all structural and spatial correlations [Yilma08,Wang09]. This is because the probability that several events occur simultaneously is equal to the product of the probabilities of the individual events under the assumption that all events are independent. However, this assumption is unrealistic and results in large errors, except for tiny delay variations in classical and mature technology nodes.
Some authors went even further and proposed measures for the "quality" or "effec- tiveness" of a test vector-pair, which are misleading even under the assumption of independent path delays. For example in [Peng10,Peng13], the authors compute the probability distributions of the path delays by a Monte-Carlo simulation. For each path that is sensitized by a test vector-pair, the probability that the delay of the path is longer than a predefined threshold, is computed. But then the authors compute the sum of these probabilities and use it as a measure of how likely a small delay fault will be detected by the test vector-pair. It can easily be seen that this is an unrealistic measure because it ignores structural and spacial correlations and the result is no longer a probability. For example, a test vector-pair which sensitizes two paths that have all but one gate in common might get a weight of e.g. 0.5+0.6=1.1, while a test vector-pair which sensitizes ten slightly shorter but mutually independent paths might get a weight of 5·0.02+5·0.01=0.15. Clearly, the latter test vector-pair is more likely to detect a randomly chosen small delay fault. Even if the path delays were mutually independent, the probability that the delay of at least one of these paths exceeds the predefined threshold would be computed by multiplication and not addition.
In the pioneering work [Ingel11], the authors introduce the "test robustness" metric for a test vector-pair, considering resistive bridging faults with uniformly distributed
resistance. Given a resistive bridging fault of random resistance that can be detected by at least one test vector-pair, the authors define the "test robustness" of a test vector-pair as the probability P(A)of the event A ∈ A in which the resistive bridging fault is detected by the test vector-pair under the impact of process variations. The authors propose to approximate this probability by computing the conditional probability P(A|Θi)of detecting the resistive bridging fault in a subset of circuit instancesΘi ⊂Θ, for a large number of pairwise disjoint subsetsΘ1 ⊂Θ, . . . , Θn ⊂Θ of circuit instance. The authors then approximate the probability of detecting the fault with the test vector-pair ("test robustness") by
P(A) ≈ n ∑ i=1P (Θi)P(A|Θi) n ∑ i=1P (Θi) , (3.1)
whereP(Θi)denotes the probability that a randomly chosen circuit instance lies inΘi. The expected error of this approximation decreases with the size of the denominator and becomes negligible if the denominator is close to 1, which can be seen as follows. Suppose that the subsets Θ1, . . . ,Θnare pairwise disjoint and Θ1∪. . .∪Θn= Θ holds, thenΘ1, . . . ,Θnis a partition ofΘ. Fromeq. (2.13)it follows that the denominator in
eq. (3.1)becomes 1 andtheorem 2.11implies the equality of both sides.
Except for mentioning a SPICE simulation, the authors don’t explicitly describe the computation of the probabilities involved in eq. (3.1) and no information about the runtime of this approach is given in the paper. Furthermore, it is questionable if the assumption of a uniformly distributed resistive bridging fault resistance is realistic. A Monte Carlo simulation based approach can naturally consider structural and spatial correlations even in very complex circuit models. However, it is well known that this approach is computationally very expensive and even requires the use of parallel hardware architectures for practical applications. For example, the authors of [Czutr12, Sauer14] compute the probability of detecting a small delay fault of fixed size with a given set of test vector-pairs under the impact of process variations by a Monte-Carlo simulation. The simulation time is reduced by simulating multiple circuit instances in parallel on a GPGPU. To avoid the large overhead of repeating the Monte-Carlo simulation of the entire test set after ever insertion or removal of a test vector-pair, the authors store the random delay values of all circuit instances together with the delay test results for all vector-pairs. However, this requires a large amount of memory. An alternative approach was taken in [Aftab09], where the authors reduce the computational cost of the Monte-Carlo simulation through compiled code simulation. However, the compile time increases rapidly with the circuit size.
After a more careful analysis of the statistical timing analysis problem, it becomes clear that a Monte-Carlo simulation of the entire circuit is unnecessary for the computation of the probability of detecting a given small delay fault of fixed size with a given set of test vector-pairs. Instead, only the critical paths (seedefinition 2.17), which are also likely sensitized by the test vector, can have a significant impact on the delay test result.
In [Lee05b], the authors propose to combine a sensitization analysis with a block based statistical timing analysis approach. At first, a single event driven timing simulation using only nominal delay values is performed with the given test vector-pair. This is done to identify the sensitized cone of the circuit on which the subsequent statistical timing analysis is applied. Afterwards, the distribution of the arrival time of the last transition at each gate output is computed using block-based statistical timing analysis. However, this approach uses the normal distribution based SUM and MAX-operation and therefore requires, that all gate delays have a normal distribution. This requirement is not satisfied in low power applications, where the gate delays are more accurately approximated by a log-normal distribution [Hanso05]. Furthermore, the distribution of the size of small delay faults is widely believed to be similar to an exponential distribution [Nigh00,Hopsc10].