All of the samples described below were fabricated in the Tyndall National Insti- tute, where transmission electron microscopy (TEM) and C-V measurements and analysis were also performed.9
Al-Silicide Samples
High quality thermally grown SiO2 layers, with a thickness of 8 nm, were grown
using a dry oxidation process in a furnace at 850 ◦C on both n (2-4 Ωcm, 1x1015 cm−3 Phosphorus) and p (10-20 Ωcm, 1x1015 cm−3 Boron) doped silicon(100)
substrates following a standard silicon surface clean. The samples were capped with 5 nm Al blanket films by electron beam evaporation. These samples were either left unannealed or annealed at 350 or 450◦C in a UHV system so as to limit the further oxidation of the Al cap.
HAXPES measurements were carried out on the National Institute of Stan- dards and Technology (NIST) beamline X24a at the National Synchrotron Light Source at Brookhaven National laboratory, as described in section 2.2. Samples were fixed on a grounded Al sample holder with stainless steel clips, which con- nected the front of the samples to the sample holder. The sampling depth for the HAXPES measurements is estimated to be no more than 24 nm10for the substrate
Si 1s which has a kinetic energy of 2310.5 eV for the 4150 eV photon energy used in these studies,11where the total sampling depth includes the ability to detect the
whole of the 5 nm of metal, 8 nm of oxide, and no more than 11 nm sampling depth into the Si. The sampling depths of the Si 1s for the 2140 eV, and 3000 eV photon energies are approximately 10 nm, and 15 nm respectively. The energy resolution and the method used to measure it will be described later in this chapter.
HfO
2/InGaAs Samples
The HfO2/InGaAs samples used epitaxial n (S-doped at 4x1017 cm−3) and p (Zn-
doped at 4x1017 cm−3) In
0.53Ga0.47As (hereafter referred to as InGaAs), grown on
lattice matched InP. The InGaAs surfaces were initially degreased by sequentially rinsing for 1 minute each in acetone, methanol, and isopropanol. The InGaAs samples were immersed in (NH4)2S solutions (10% in deionized H2O) for 20 minutes
at room temperature (295 K), which was found to be the optimum approach to suppress the formation of native oxides and to reduce the high-κ/III-V interface state density, as reported previously.12 Samples were then introduced to the atomic
layer deposition (ALD) chamber load lock after the removal from the 10% (NH4)2S
surface passivation solution. The transfer time from the aqueous (NH4)2S solution
to the ALD chamber was kept to a minimum (3 minutes) in order to minimise the formation of native oxides resulting from air exposure.
The 5 nm HfO2 was deposited by ALD at 250 ◦C using Hf[N(CH3)C2H5]4
(TEMAH) and H2O precursors. Some samples were left without a metal gate,
while others were capped with 5 nm Al or Pt blanket films. All metal depositions were achieved by electron beam evaporation. Additional samples were produced for electrical characterisation analysis in an identical fashion to that mentioned above, although the metal caps were 110 nm thick so that they could be used as contacts in the C-V measurement process. The metal gate areas for C-V characterisation were defined by a lithography and lift-off process.
SiO
2/Si Samples
The SiO2/Si based MOS structures were prepared in an identical manner to the
Al-silicide samples previously described, with the exception that some samples were left without metal gates and some were capped with 5 nm Ni blanket films by electron beam evaporation instead of Al, as shown in figure 3.1. The sample set measured by HAXPES is shown in table 3.1. For electrical characterisation, Ni/Au (90 nm/70 nm) and Al (160 nm) gate electrodes were formed by electron beam evaporation and a lift off lithography process. The Si/SiO2 samples did not
Figure 3.1: SiO2/Si samples for HAXPES and C-V characterisation. Si substrates
were capped with an 8 nm SiO2 layer and either left without a metal gate or
capped with a 5 nm Al or Ni gate.
Substrate Dopant type Dielectric Metal
Si n-type SiO2 (8 nm) none
Si n-type SiO2 (8 nm) Al (5 nm)
Si n-type SiO2 (8 nm) Ni (5 nm)
Si p-type SiO2 (8 nm) none
Si p-type SiO2 (8 nm) Al (5 nm)
Si p-type SiO2 (8 nm) Ni (5 nm)
Table 3.1: SiO2/Si samples for HAXPES analysis
receive a final forming gas (H2/N2) anneal.
In order to ensure correct energy calibration throughout the experiment, metal- lic Ni Fermi edge reference spectra were acquired immediately before and after the acquisition of the SiO2 and Si substrate core level peaks. The resultant error as-
sociated with this photon energy correction procedure is estimated to be no more than ±50 meV. The maximum depletion region width for the 1x1015cm−3 doped Si
substrate is 800 nm, and the total sampling depth of the HAXPES measurements is estimated to be no more than 23 nm10for the substrate Si 1s which has a kinetic
energy of 2310.5 eV for the 4150 eV photon energy used in these studies.11 The
total sampling depth includes the ability to detect the whole of the 5 nm of metal, 8 nm of oxide, and no more than 11 nm sampling depth into the Si. Therefore,
of the Fermi level in the silicon at the SiO2/Si interface i.e. the surface Fermi
level position. However, it is noted that for Si samples in inversion, which exhibit strong surface band-bending, the sampling depth of the HAXPES may cause the peaks to shift by up to 0.1 eV to lower BE.13
The C-V measurements were recorded using an Aligent C-V-enabled B1500A semiconductor device analyser following an open correction and performed in a Cascade Microtech probe station (model Submit 12971B) in a dry air, dark envi- ronment. The B1500A analyser allows for C-V measurements performed at a wide range of AC frequencies (1 kHz to 5 MHz). All the C-V responses were measured starting from inversion and sweeping towards accumulation in order to reduce the effect of border traps, which shift the measured C-V curve.14 An AC frequency of 1 MHz was used in order to minimise the contribution of an interface state ca- pacitance to the overall capacitance of the MOS capacitor. Under this condition, the primary effect of the interface states is to stretch out the C-V along the gate voltage axis so that Fermi level position can be determined, using the measured capacitance providing that the MOS capacitor is in depletion at Vg = 0 V. Multi-
ple sites with different areas were examined in order to ensure the C-V results are representative of the sample behaviour.