Shown in Figure 4.30 is a die-photo of a prototype merged two-stage converter fabricated in National Semiconductor’s CMO9T5V 180 nm CMOS process, with 6 metal layers. Because of packaging restrictions, the die was connected through bond-wire (with considerably higher resistance than a flip-chip packaging method) to the LLP40 5x5 mm package. 1.3 mil gold bond-wire was used, with all pins processing power double-bonded to decrease the parasitic resistance. The layout was optimized to minimize bond-wire and on-chip metallization
4.6 Experimental Results
Switched−Capacitor
Power
Switches
Buck
Gate
Drive
Buck
Control
Control
SC
Power Switches and Gate Drives
Figure 4.30: Die photograph of a soft charging converter implemented in 180 nm CMOS technology. The total die area is 5x5 mm (not optimized for space).
resistance as much as possible, which lead to an overall design with larger area than what was actually required by the power devices. As can be seen from the die-photo, all power devices are placed at the perimeter of the chip, and placed as to minimize interconnect distances.
The chip was mounted on a test PCB, as shown in Figure 4.31. In addition to the passive off-chip components directly required by the merged two-stage converter, the test PCB also contains a micro-controller (ATtiny861) that writes serial data to the chip for setting parameter values, as well as enable/disable select parts. A Python script on a lab bench computer communicates over serial interface with the micro-controller. The test PCB also contains tuning potentiometers for setting reference voltages, as well as floating current sources for biasing purposes.
180 nm CMOS Integrated Merged Two Stage Converter
Floating current mirrors
Micro−controller
Tuning potentiometers
Two−stage Converter
Figure 4.31: Photograph of test PCB with bias current sources, reference voltages, and a micro- controller to write parameter settings to the chip.
Figure 4.32 shows a zoomed-in photograph of the merged two-stage test chip, as well as the passive components. The SC stage external capacitors (C1 and C2) are placed on the
bottom side of the PCB to minimize the loop area.
Despite our best efforts to keep packaging losses to a minimum, upon testing it was discovered that bond-wire resistance and on-die metallization resistance were significantly higher than anticipated. This has a particularly detrimental effect on efficiency at high output powers, where the ohmic losses dominate. For this reason, the output level at which we run our converter (up to 0.8 W) is lower than the 2 W that it was designed to handle. Furthermore, although the buck regulator stage was designed to operate at 30 MHz, the new lower power level required a decrease in switching frequency to 10 MHz to maintain satisfactory efficiency. This was due to the fact that the power switches in the buck regulator were sized for 2 W max output load, and at the lower output power the gating loss became a dominant loss that decreased efficiency. It should be mentioned that the buck regulator works at a switching frequency up to 30 MHz, at the expense of efficiency. For the experimental results shown in this work, the operation and characterization was done at a regulation stage frequency of 10 MHz.
4.6 Experimental Results
Test Chip
C
L
Cin, sc
out, buck
buck
Figure 4.32: Photograph of merged two-stage test chip mounted on PCB, along withi top-side passive components. Some capacitors were placed on the bottom side to minimize inductance.
Table 4.4: Converter Specifications Input Voltage Range 4.5-5 V
Output Voltage Range 1-1.3 V Output Power Range 0.3-0.8 W
SC Switching Frequency 2-100 kHz (load dependent) Buck Switching Frequency 10 MHz
Peak Efficiency 81%
Shown in Table 4.4 is a table that summarizes the operation region and performance of the experimental prototype. The efficiency includes all control and gating losses of the two converters.
Shown in Fig. 4.33 are experimental waveforms that illustrate the performance of the feed-forward control circuitry. It can be seen that despite large voltage swings at the input of the buck converter (>500 mV step of Vunreg), the output voltage remains stable (<50
mV ripple). It should be noted that this was accomplished without a large capacitor on the output of the buck regulator as can be seen in Table 4.5, which lists the external components used in the experimental prototype. The good attenuation of the input ripple can be attributed to the feed-forward control, which works well. For this measurement, the
180 nm CMOS Integrated Merged Two Stage Converter
Table 4.5: External Component Values Component Value Type
Cin,SC 3 x 10 µF X5R, 0603
C1 22 µF X5R, 0603
C2 22 µF X5R, 0603
Cin,buck 2 µF X5R, 0402
Cout,buck 4.7 µF X5R, 0402
Lbuck 28 nH Air core, Coilcraft B08T
input current to the ramp generator (Iramp, which controls frequency), was set to 13.8 µA,
and the bias current of the transconductance amplifier (Ibias of Figure 4.22) was 0.7 µA.
The performance of the converter was also evaluated during a load-step, as shown in Figure 4.34. Here the load was stepped repeatedly between 10% and 90% of full load, using a switchable external resistor load. This type of load behavior is possible when electronic circuit go in and out of sleep mode, for instance. It can be seen from the waveform that the control implementation maintains the output voltage at the desired operating point, despite both load steps and large buck converter input voltage. The light-load operation of the SC stage is also apparent in this plot, where the hysteretic controller increases the switching frequency of the SC stage at heavy load, and reduces it at light load (leading to lower loss at light load).
Measured efficiency for a few different output voltages are shown in Fig. 4.35. The efficiency measurements include all power losses associated with the control circuitry, as well as gating losses and all packaging and bond-wire losses. The decrease in efficiency at low input power is almost entirely due to the regulation stage, which was operated at a fixed frequency (10 MHz) at all times. Efficiency at low power levels can be increased with suitable light-load control schemes such as pulse-frequency modulation (PFM), if desired. The SC stage is inherently light-load efficient due to the hysteretic controller, which automatically operates at a lower switching frequency at low output power.
4.6 Experimental Results
Vout − ac coupled 50 mV/div
Vout − dc coupled 1 V/div Vunreg − dc coupled 500 mV/div
Vin − dc coupled 5V/div
Figure 4.33: Experimental waveforms showing converter operation. Note that the input voltage is 4.5 V, and the output voltage is steady at 1 V, despite the large voltage swings at the input of the buck converter (Vunreg).
Table 4.6 shows an estimated breakdown of losses. A significant portion of the losses come from bond-wire resistance and on-chip metallization resistance, owing to the package used. There are well-known techniques to mitigate these losses (e.g thick top layer metallization, flip-chip technology). It is therefore expected that the overall converter efficiency can be significantly improved through appropriate packaging techniques.
Shown in Fig 4.36 is the measured efficiency of the merged two-stage converter together with modelled efficiency for a single-stage buck converter operating at 10 MHz. The single- stage buck converter is modelled with the same 5 V devices (and attendant packaging losses) that were used in the SC stage, and provides a benchmark for comparison. It should be noted that only gate drive and conduction losses (including packaging) were modelled, and that an experimental implementation would likely see an even lower measured efficiency than what is shown in Fig 4.36, owing to additional control and switching losses. Moreover, while a switching frequency of 10 MHz is approaching the practical limit of a single-stage 5-to-1 V buck converter, the merged two-stage converter can be operated at
180 nm CMOS Integrated Merged Two Stage Converter
Load−step command signal Vunreg − dc coupled 500 mV/div
Vin − dc coupled 5V/div
Vout − ac coupled 100 mV/div
Figure 4.34: Experimental waveforms showing converter operation performance during a load step between 10 and 90% of full load. The output voltage is steady, and the light-load behavior of the SC stage can be observed.
even higher switching frequencies without difficulty, owing to its use of low-voltage devices in the regulation stage. The more important result, however, is that compared to a single- stage topology, the two-stage architecture that we have presented scales well to significantly higher switching frequencies than what was demonstrated here. Consequently, we expect the benefits in terms of size and efficiency of our proposed architecture to be even more apparent as higher switching frequencies are pursued.
Table 4.6: Estimated Converter Loss Breakdown at Pout=0.8 W Bond-wire conduction loss 60 mW
Transistor gating loss 45 mW On-die metallization conduction loss 40 mW Transistor conduction loss 11 mW
Inductor loss 5 mW
4.7 Conclusions