Manufacturing test employs fault models and fault simulation to test digital ICs to ensure that they operate as intended and meet the desired specification. Fault models are used to capture the defect behaviour to determine the error of the corresponding defects at the output of the circuit under test. Fault simulation simulates the behaviour of a circuit in the presence of faults, and compares the results with fault-free circuit to determine fault detection. The following sub-sections give a brief introduction to fault models and fault simulation, and a discussion of fault modelling and fault simulation using SPICE.
1.3.1 Fault Models
Fault models are used to model the behaviour of physical defects at the device level. They are developed and employed to predict how faults occur and the impact of these faults
on circuit behaviour. The complexity of defect behaviour analysis is greatly reduced by modelling the physical defects as fault models. For example, when a defect is modelled as a logical fault, the analysis of the defect can be explained in logical terms. In addition, many physical defects can be modelled by the same fault model thus reducing the number of individual defects that have to be considered. A fault model is a formal description of how a defect causes the faulty behaviour in a circuit. It typically specifies the faulty behaviour that can occur and where such behaviour can occur. That means the fault model identifies the possible fault locations and predicts the number of possible faults in a given circuit. By knowing the number of faults and their locations in a circuit, the quality of a given test can be evaluated through the ratio of the detected number of faults to the total number of considered faults (fault domain), which is called the fault coverage. The fault coverage is represented in Eq.1.4. One hundred per cent fault coverage means that all possible fault locations that are specified by the fault model can be detected. Fault models are important for manufacturing test because fault simulation, diagnosis and test generation are all built around fault models. Fault simulation is based on fault models and are meant to measure the fault coverage (Eq.1.4). Test patterns are guided by fault models to generate the required test to excite and propagate the faults to primary output(s). The quality of generated test is evaluated through fault coverage.
F C = DetectedF aults
T otalF aults × 100 (1.4)
Fault models are used to study and simulate the behaviour of physical defects. There are many different physical defects, for example, bridges, opens, transmission gate open [71,
72], gate oxide shorts [73], threshold voltage shift [74] etc. Therefore there is no single fault model that can capture the impact of each one of these at higher level of abstraction. This is why test is generated considering a number of defects and their respective fault models. Some well-known and commonly used fault models are:
• Stuck-at fault: This models the defects that cause a logic signal that connected to one of the power rails, i.e., Vdd or GND, causing the logic node to be clamped
at the voltage of the rail [59]. This fault model has two faulty behaviours which are referred to as “stuck-at 0” or “stuck-at 1”. Stuck-at 0 describes a node that is connected to the ground rail while stuck-at 1 is a node that is connected to the power rail (Vdd). The stuck-at fault model is one of the most widely-used
fault models for test generation. It can be used to detect many different physical defects, such as bridges and opens at a part of the fault domain.
• Stuck-open and Stuck-short fault: Stuck-open models the behaviour of a transistor where drain or source is disconnected inside a gate leading to faulty behaviour [75]. The detection of stuck-open fault need two test vectors: the first one drives the output logic of a gate to logic high or low, while the second one
uses a transistor in the pull-up or pull-down network of a gate to drive the output logic value to the opposite value [59]. Stuck-short fault models a conducting path between Vdd and ground that may be detected by using IDDQ test [76].
• Bridging and Open fault: The bridging fault models a physical scenario where interconnect lines are accidentally connected with one another, thereby deviating the circuit behaviour from ideal [59]. The bridge fault is excited only by driving two connected lines at opposite logic values. The open fault models a physical scenario where the connection breaks between the two nodes in a manufactured circuit that should be connected and therefore causes the circuit to deviate from its ideal behaviour.
• Delay fault: The delay fault models the behaviour caused by physical defects or process variation that cause additional circuit delay, which can lead to the circuit failing to meet the performance requirements (e.g. a specified clock period). The delay is the time interval that measures on a gate or a path from one logic state to another logic state. It can be gate transition delay or path delay. The gate transition delay fault models the behaviour of a signal while propagating through a gate if a signal violates its timing due to excessive delay through the gate [77]. The path delay fault models the cumulative delay of a path to include gates and interconnects that exist in that path of a circuit [78]. A small delay fault is a class of path delay fault and it models defects that lie outside the critical path in a circuit and normally introduce less than one clock cycle delay [68, 69]. Due to overlap between fault detection using different fault models, a test to detect delay faults may also detect stuck-at faults or bridging faults. This is why manufacturing test commonly applies tests targeting delay faults first, followed by stuck-at faults, bridge faults and finally transistor level stuck-open faults to achieve a high fault coverage in the minimum possible test application time [51].
1.3.2 Fault Simulation
Fault simulation plays an important role in manufacturing test. This is because many test generation techniques use fault simulation to evaluate a generated test set T S through fault coverage (Eq.1.4). Fault simulation simulates the faulty output responses of a circuit based on targeted fault models, and the fault simulation results with applied test set T S are compared to results that come from the fault-free circuit with the same test T S to determine the fault coverage of T S. T S is changed according to the results of the fault simulation until the obtained coverage is considered satisfactory. A fault simulation in manufacturing test normally consist of the following five tasks:
• Fault-free simulation: simulation on fault-free circuit to record fault-free output response and then it is used to compare output responses from the faulty circuit.
• Fault specification: generate a list of targeted faults at a given circuit.
• Fault insertion: select a subset of faults to be simulated and use corresponding fault models to indicate the detection of faults.
• Fault propagation: generate faulty behaviour through fault insertion and prop- agate the faulty behaviour to primary outputs.
• Fault detection: evaluate the fault detection through fault coverage. If the fault coverage is considered satisfactory, the detected faults are discarded from the fault list to indicate that the fault can be detected with the specific test set T S. The remaining undetected faults are targeted in the next round of test generation.
Fault simulation is also used to analyse the behaviour of a circuit in the presence of defects for better modelling of defects and generation of test to detect faults caused by defects. Another application of fault simulation is to construct pre-generated databases for test generation [26]. Normally, a pre-generated database stores the output response to test set T S of every faulty circuit corresponding to targeted fault models. Using a database with every possible faulty output response to test digital ICs can help in reducing test time, for example, using a histogram database as developed in [79,80]. It is also used for test compaction database [81,82].
1.3.3 Fault Modelling and Simulation in SPICE
One of the commonly used approaches in fault modelling and fault simulation is SPICE. SPICE (Simulation Program with Integrated Circuit Emphasis) is a computer simulation and modelling program used to mathematically predict the behaviour of electronics cir- cuits. It was initially developed at the University of California at Berkeley. The current commercial versions of SPICE include Synopsys HSPICE [83] and Cadence PSPICE [84], there is also an open source version of SPICE called NGSPICE [85]. SPICE can be used to simulate electrical circuits in steady-state (DC simulation), transient (TRAN simu- lation), and frequency domains (AC simulation). Fault modelling and fault simulation using SPICE is the most accurate method of modelling and simulating faulty behaviour of a circuit in the presence of defects. SPICE simulation is accurate because SPICE employs advanced convergence algorithms to achieve results within the specified accu- racy tolerance and sophisticated semiconductor device models such as BSIM4 MOSFET models [86] to accurately simulate the device behaviour in a circuit. Fault modelling using SPICE can be summarised as:
1. Insert physical defect description into a circuit netlist;
2. Simulate circuit behaviour in the presence of defects using DC, TRAN or AC simulation;
3. Analyse faulty output behaviour of the defective circuit;
4. Create data structures or functional description as fault models to model the faulty behaviour caused by the defects;
5. Use the created data structures or functional description in fault simulation to indicate the fault detection.
Recent researches reported in [2, 10, 80] indicate that modelling the impact of pro- cess variation on deep submicron defects through SPICE is the most accurate method. SPICE uses Monte-Carlo simulation to model variation on device parameters. Monte- Carlo simulation generates random values for the targeted device parameters by follow- ing the specific distributions (i.e. Gaussian distribution as shown in Eq. 1.1) in each repeated simulation. Every repeated simulation contains a set of values for the targeted device parameters. A set of values is also called a sample. By increasing the number of samples, the simulated effect of variation can capture more possible behaviours caused by variation. Monte-Carlo simulation normally uses a large number of samples to cap- ture the effect of variation, therefore leading to a long simulation time in SPICE. A detailed SPICE simulation flow of DC and TRAN simulation with Monte-Carlo analysis is shown in AppendixA.