RSER
Note: This figure shows a typical application where two DS26521s are on a single 4.096MHz backplane.
8.8.3 H.100 (CT Bus) Compatibility
The registers used for controlling the H.100 backplane are RIOCR and TIOCR.
The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26521 to accept a CT bus-compatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs.
The following rules apply to the H100EN control bit.
1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input mode) only. The RSYNC output and other sync signals are not affected.
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz IBO mode or 2.048MHz backplane operation.
4) The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for the TSSYNCIO).
5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must be set high to invert the inbound sync signals.
Figure 8-12. RSYNC Input in H.100 (CT Bus) Mode
BIT 8 BIT 1 BIT 2
RSYNC1
RSYNC2
RSYSCLK
RSER
tBC3
NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION.
NOTE 2: RSYNC INPUT MODE, H.100EN = 1 AND RSYNCINV = 1.
NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns or 488ns ALSO ACCEPTABLE.
Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode
8.8.4 Receive and Transmit Channel Blocking Registers
The Receive Channel Blocking registers (RCBR1:RCBR4) and the Transmit Channel Blocking registers (TCBR1:TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to 1, the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. When used with a T1 (1.544MHz) backplane, only TCBR1:TCBR2:TCBR3 are used. TCBR4 is included to support an E1 (2.048MHz) backplane when the elastic store is configured for T1-to-E1 rate conversion. See Section 8.8.1.
8.8.5 Transmit Fractional Support (Gapped Clock Mode)
The DS26521 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled via the Transmit Gapped-Clock Channel Select registers (TGCCS1:TGCCS4). The transmit path is enabled for gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
8.8.6 Receive Fractional Support (Gapped Clock Mode)
The DS26521 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled via the Receive Gapped-Clock Channel Select registers (RGCCS1:RGCCS4). The receive path is enabled for gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
BIT 8 BIT 1 BIT 2
TSSYNCIO1
TSSYNCIO2
TSYSCLK
TSER
tBC 3
NOTE 1: TSSYNCIO IN NORMAL OPERATION.
NOTE 2: TSSYNCIO WITH H.100EN = 1 and TSSYNCINV = 1.
NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns OR 488ns ALSO ACCEPTABLE.
8.9 Framers
The DS26521 framer core is software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding, synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides clock/data and frame-sync signals to the backplane interface section. Diagnostic capabilities include loopbacks, and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access and control of the device.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS (zero code suppression) and AMI line coding.
Both the transmit and receive path have an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller can be assigned to any time slot, portion of a time slot, or to FDL (T1). The HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An IBO is provided to allow multiple framers in the DS26521 to share a high-speed backplane.
8.9.1 T1 Framing
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit contains a fixed pattern for the receiver to delineate the frame boundaries. The F-bit is inserted once per frame at the beginning of the transmit frame boundary. The frames are further grouped into bundles of frames 12 for D4 and 24 for ESF.
The D4 and ESF framing modes are outlined in Table 8-5 and Table 8-6. In the D4 mode, framing bit for frame 12 is ignored if Japanese Yellow is selected.