In general, the file operations allowed are limited. Files cannot be opened, closed, or accessed in a random sequence. All that VHDL pro- vides is a simple sequential capability. See Appendix D for a description of VHDHL93 file access. For textual input and output, there is another facility that VHDL provides called TextIO. This facility provides for formatted textual input and output and is discussed in Chapter 8, “Advanced Topics.”
Subtypes
Subtype declarations are used to define subsets of a type. The subset can contain the entire range of the base type but does not necessarily need to. A typical subtype adds a constraint or constraints to an existing type.
The type integer encompasses the minimum range -2,147,483,647 to
2,147,483,647. In the Standard package (a designer should never redefine any of the types used in the Standard package; this can result in incom- patible VHDL, because of type mismatches), there is a subtype called NAT- URALwhose range is from 0 to 2,147,483,647. This subtype is defined as shown here:
TYPE INTEGER IS -2,147,483,647 TO 2,147,483,647; SUBTYPE NATURAL IS INTEGER RANGE 0 TO 2,147,483,647; After the keyword SUBTYPEis the name of the new subtype being created. The keyword ISis followed by the base type of the subtype. In this exam- ple, the base type is INTEGER. An optional constraint on the base type is also specified.
So why would a designer want to create a subtype? There are two main reasons for doing so:
■ To add constraints for selected signal assignment statements or case statements.
■ To create a resolved subtype. (Resolved types are discussed along with resolution functions in Chapter 5.)
When a subtype of the base type is used, the range of the base type can be constrained to be what is needed for a particular operation. Any functions that work with the base type also work with the subtype.
Subtypes and base types also allow assignment between the two types. A subtype can always be assigned to the base type because the range of the subtype is always less than or equal to the range of the base type. The base type may or may not be able to be assigned to the subtype, depending on the value of the object of the base type. If the value is within the value of the subtype, then the assignment succeeds; otherwise, a range constraint error results.
A typical example where a subtype is useful is adding a constraint to a numeric base type. In the previous example, the NATURALsubtype con- strained the integer base type to the positive values and zero. But what if this range is still too large? The constraint specified can be a user- defined expression that matches the type of the base type. In the following example, an 8-bit multiplexer is modeled with a much smaller constraint on the integer type:
PACKAGE mux_types IS
SUBTYPE eightval IS INTEGER RANGE 0 TO 7; --line 1 END mux_types;
USE WORK.mux_types.ALL; LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY mux8 IS
PORT(I0, I1, I2, I3, I4, I5, PORT(I6, I7: IN std_logic;
PORT(sel : IN eightval; --line 2 PORT(q : OUT std_logic);
END mux8;
ARCHITECTURE mux8 OF mux8 IS BEGIN
WITH sel SELECT --line 3
Q <= I0 AFTER 10 ns WHEN 0, --line 4 Q <= I1 AFTER 10 ns WHEN 1, --line 5 Q <= I2 AFTER 10 ns WHEN 2, --line 6 Q <= I3 AFTER 10 ns WHEN 3, --line 7 Q <= I4 AFTER 10 ns WHEN 4, --line 8 Q <= I5 AFTER 10 ns WHEN 5, --line 9 Q <= I6 AFTER 10 ns WHEN 6, --line 10 Q <= I7 AFTER 10 ns WHEN 7; --line 11 END mux8;
The package mux_typesdeclares a subtype eightval, which adds a con- straint to base type INTEGER. The constraint allows an object of eightval to take on values from 0 to 7.
The package is included in entity mux8, which has one of its input ports seldeclared using type eightval. In the architecture at line 3, a selected signal assignment statement uses the value of selto determine which output is transferred to the output Q. If selwas not of the sub- type eightval, but was strictly an integer type, then the selected signal assignment would need a value to assign for each value of the type, or an OTHERSclause. By adding the constraint to the integer type, all values of the type can be directly specified.
SUMMARY
In this chapter, we have examined the different types available in VHDL to the designer. We discussed the following:
■ How types can be used by three different types of objects: the signal, variable, and constant.
■ How signals are the main mechanism for the connection of entities, and how signals are used to pass information between entities.
■ How variables are local to processes and subprograms and are used mainly as scratch pad areas for local calculations.
■ How constants name a particular value of a type.
■ How integers behave like mathematical integers, and real numbers behave like mathematical real numbers.
■ How enumerated types can be used to describe user-defined operations and make a model much more readable.
■ How physical types represent physical quantities such as distance, current, time, and so on.
■ The composite type, arrays and records. Arrays are a group of elements of the same type, and records are a group of elements of any type(s).
■ How access types are like pointers in typical programming languages.
■ How file types are linear streams of data of a particular type that can be read and written from a model.
■ How subtypes can add constraints to a type.
In the next chapter, we focus on another method of sequential statement modeling: the subprogram.