4-1. INTRODUCTION
This chapter describes the Mark V LM software and hardware structure and overall operation of the control panel. Refer to the sample connection diagrams in Appendix B. Chapter 5 contains descriptions of the printed wiring boards in the control panel.
4-2. HARDWARE STRUCTURE
The Mark V LM control panel consists of several cores. Cores are sheetmetal housings that can have stationary and moveable printed wiring board holders called card carriers. The cores have a maximum of five printed wiring boards mounted on the card carriers. In addition, up to four high density I/O terminal boards can be mounted on a single core. The combinations of boards contained in each core is dependent on the application. See Figure 1-1 for a picture of a typical Mark V LM core layout.
Note
The terms card and board both apply to the printed wiring boards. In this manual, board is the preferred term. However, card is used in some drawings and terms if it is pre-established nomenclature – for example, card carrier.
The Control Engine core, or <CE> core is the main control processor that is used to protect, monitor, and control the unit and to communicate to the operator interfaces. This core is commonly known as the <R> core. The <R> core contains a powerful 486DX CPU with companion circuitry to process the application software. The <R> core contains the following printed wiring boards:
• UCIA – Motherboard where the UCPB, PANA, and µGENI boards are mounted. Contains a 196 processor that translates pressure transducer signals from the TCSA board for the UCPB board to use.
• UCPB – Daughter board on the UCIA mother board that contains the 486DX processor, or CPU, and the ARCNET driver for external communications with the operator interfaces. Used in conjunction with the AAHA board.
• TCSA – Optional board for Dry Low Emissions (DLE) applications. Contains decoders for communication between the XDSA board on the fuel skid and the UCIA board in the <R> core.
• TCPS – Power supply board.
• PANA – The ARCNET driver for internal communications with the I/O cores. Mounted as a daughter board to the UCIA board.
• AAHA – Board with two BNC connectors for ARCNET communication. Used for the Stage Link connections on the <R>
core via the UCPB board, and for the COREBUS connections between the <R> core and the I/O Cores via the PANA board.
Other cores associated with a typical Mark V LM control panel include protective core, <P1> ; a power distribution core, <PD>;
I/O cores, <R1>, <R2>, <R3>,and <R5>; and two digital I/O cores, <Q11> and <Q51>.
The <P1> core contains protective processors. Each of these processors are responsible for emergency overspeed detection and trip signal initiation, provide ultraviolet flame detector excitation voltage, and synchronization for generator drive applications.
The status in each board of these functions are voted using a “two out of three” process and the voted value is used in the protection algorithms/sequencing. The <P1> core contains the following printed wiring boards:
• TCEA – Contains the microprocessor circuitry for critical protection, known as the “protective processors”.
• TCEB – Expander board for the TCEA’s.
• TCTG – The trip board which contains the units trip solenoids.
• PTBA – Protective core terminal board.
The I/O cores are used to read and write analog signals. These cores contain the I/O Engine, a 486DX CPU with companion circuitry, that is used to communicate the I/O signals to the <R> core. Microprocessors on the TCQA, TCQC, TCQE, TCCA and TCCB boards scale and condition the analog signals using I/O configuration information contained on the core’s RAM. The data is then sent across the COREBUS to the Control Engine in the <R> core and into the Control Signal Database located in that core. After the signals have been used in the application software, the results are then sent back across the COREBUS to the I/O cores. These cores contain combinations of the following printed wiring boards:
• STCA – IONET master for the I/O cores. Performs I/O configuration on some signals. Provides synchronization check.
UCPB board is mounted on this board.
• UCPB – Contains a 486DX CPU used as the I/O engine.
• TCQA, TCQE, TCCA, and TCCB – I/O boards containing the I/O configuration software.
• TCPS – Power supply board.
• TCQC – Contains the I/O expansion for the TCQA board and the IONET communication interface from <R1> to <Q11>and
<P1>.
• QTBA – Terminal Board that contains the COREBUS communications and I/O termination’s in <R1>, <R2>, and <R3>.
• CTBA – Terminal Board that contains IONET and COREBUS communication interface and I/O termination’s in <R5>.
• TBQA, TBQB, TBQC, TBQE, TBCB, and TBCA, TB3 – I/O terminal boards.
The two digital I/O cores, <Q11> and <Q51>, are used to read and write digital I/O signals. These cores send their data through an I/O communication network, (IONET), to either cores <R1> or <R5> for transmission. The digital I/O cores contain the following printed wiring boards:
• TCDA – Conditions the digital I/O signals and communicates to the I/O cores through the IONET.
• TCRA – Relay board.
The <PD> core is used to distribute the 125 V dc to the TCPS power supply boards located in each I/O core and in the Control Engine core, <R>, to the TCEA boards and the TCTG board in the <P1> core and to the DTBA, DTBC and DTBD terminal boards in the digital I/O cores. The <PD> core contains the following printed wiring board:
• TCPD – Contains the circuitry that distributes the 125 V dc.
Section 4-4 contains the overall operation of the Mark V LM. Chapter 5 describes the function and operation of the printed wiring boards. Appendix C contains the Power Distribution Core diagrams.
4-3. APPLICATION SOFTWARE STRUCTURE
The Mark V LM controller stores on the hard drive or flash memory in the <R> core the application specific control software, operating system and control constants and loads them on to RAM when the <R> core is rebooted. The 486DX CPU calls the Control Sequence Program (CSP), associated Big Blocks, and Control Constants from the RAM as they are used. The 486DX CPU in <R> controls memory access to the Control Signal Database. The Control Signal Database is an area of memory reserved in the <R> core’s RAM for storage of values that are used by the sequencing program and for viewing by the operator interfaces.
Major elements of the software configuration are:
• Use of functional blocks, or Big Blocks, for specific control, monitoring and protection of the unit.
• Use of Relay Ladder Logic to build the control sequencing.
• Use of the control signals names that correspond to memory locations in the panels RAM that are used for calculations, I/O values, control constants and alarms.
• Use of the constants that are the parameters for I/O configuration, unit control and process alarms.
4-3.1. Big Block System
The Control Sequence Program (CSP), used by the Mark V LM as its application software, uses a programming language known as Big Block Language, or BBL. BBL is a relay ladder logic based software structure that defines data flow and function execution. The software structure is made up of a series of rungs that can contain combinations of comments, contacts, coils and Big Blocks. Big Blocks are software modules that perform standardized control functions.
There are three different types of Big Blocks: Primitive, Generic and Application Specific. Primitive blocks perform simple functions such as add and multiply. These blocks can be added to the end of a rung of ladder logic. Generic blocks are more complex, and can only be used in a rung by themselves. Application Specific blocks are used for certain control applications. Big Blocks are located on the hard drive or flash memory in the <R> controller and loaded onto RAM on startup of the controller for execution. CSP’s downloaded to the Control Engine call the Big Blocks as needed.
The Control Sequence Editor can be used to create new CSP’s or to edit existing ones. The Control Sequence Editor has an on line help system available. The operator interface manual explains the use of the Control Sequence Editor as well as the BBL
language itself.
4-4. CONTROLLER OPERATION
The Mark V LM provides programmable microprocessor unit control and protection. Control parameters are stored in RAM.
Field signals are brought in through the various terminal boards on the I/O cores, digital I/O cores and the protective core. In the digital cores, the TCDA board scales and conditions the signals and sends them via the IONET to the I/O cores <R1> and <R5>
through the TCQC board and CTBA terminal board respectively. The signals from the TCEA boards in the <P1> core are also sent across the IONET to the <R1> core. The analog signals are brought directly into the terminal boards of the I/O cores and are scaled and conditioned by the TCQA, TCQC, TCQE, TCCA and/or TCCB boards. All of the I/O signals are sent to <R> across the COREBUS through the QTBA or CTBA terminal boards.
The I/O configuration constants are sent from RAM in the <R> core to the I/O cores 486DX CPU (I/O Engine) via the
COREBUS. The I/O Engine stores the configuration constants on RAM located on the I/O boards in the I/O cores and the digital I/O cores on rebooting of the cores. Microprocessors on the I/O boards use the configuration constants along with the
configuration software to perform the scaling and conditioning of all the I/O signals read from the terminal boards. The I/O Engine sends the calculated values across the IONET. The I/O boards also scale and condition the values to be written to the terminal boards as outputs. See Chapters 6 and 7 for the Mark V LM’s I/O specifications and applications and the operator interface manual for more information on the I/O Configurator.
The Control Sequence Program (CSP), Control Constants, and I/O Configuration Constants are downloaded from the operator interface across an ARCNET communication link, called the Stage Link, located on the AAHA board. The Stage Link downloads these files to the Control Engine, a 486DX CPU located on the UCIA/UCPB board in the <R> core. The Control Engine is responsible for sending the I/O Configuration Constants across the COREBUS to the I/O Engines in the I/O cores, running the CSP, and for storing values in the Control Signal Database memory locations.
Communication transfers and frame rates are generally done at 100 Hz, (10 ms). QNX is the operating system for the Control Engine. The Control Engine converts the fixed point I/O signals obtained from the COREBUS to floating point values for use in the application software. The Control Engine also converts the values back to fixed point for transfer back across the COREBUS to the I/O cores and digital I/O cores. Some additional scaling is done by the Control Engine during these conversions. More information on the communication networks can be found in Chapter 1 of this manual.
4-5. CORE CONNECTION DRAWINGS
Appendix B contains sections of sample Hardware Documents showing the core interconnection diagrams. Site specific Hardware documents are shipped with each Control Panel.