Low-Power Very Fast Dynamic Logic Circuits
8.5 The Future of Dynamic Logic
It is well-known that dynamic CMOS logic circuits suffer from the leakage current, which puts a limit on the minimum possible clock frequency. This became a serious problem in deep submicron technol-ogies. When VDD is scaled down, VTH, the threshold voltage, has to be scaled down to not lose the advantage of scaling, which is associated with the exponential increase in subthreshold leakage current [25]. It not only limits the use of dynamic logic but also dominates the overall power consumption. Advanced leakage control methods will become indispensable for future technologies [26].
Fortunately, some techniques have already emerged. One technique uses the self-reverse-biasing effect of stacked transistors, called stacking-effect, to reduce the standby leakage current [27]. This effect was successfully used in a low-leakage, gated-ground cache in which two off transistors connected in series reducing the leakage current by orders of magnitude [26]. It means that the topology and design methods have to change to meet the new challenge. Of course, to use static logic may avoid the reliability problem due to the leakage current; however, the reason to use dynamic logic has been its efficiency and high speed over its static counterpart under the same or a lower power budget. Therefore, dynamic logic may still find its position in deep submicron technologies if new techniques reducing the subthreshold leakage current are discovered by active researches in this field.
8.6 Conclusion
The comparisons in Table 8.1 and Figure 8.12 demonstrate that carefully designed dynamic CMOS flip-flops and latches — nonprecharged or precharged, single-ended or differential — present obvious short delays and small power-delay products over traditional dynamic and static flip-flops at different activity ratios. The strategies of single clock, low count of clocked devices, fewer transistors, nonclassic concept, and simple configurations lead to the results. The latches and flip-flops can be used in a pipeline or a double pipeline, resulting in a very high data throughput. When logic is embedded in an n-block, the number of devices and the overall capacitance is significantly less than what is necessary for a comple-mentary logic, gaining high speed and low-power advantages. Advanced circuit topologies presented in the examples of functional circuits make the dynamic logic circuits highly attractive; however, precautions have to be taken. The robustness of dynamic (especially precharged) logic against power and ground noises is not as good as complementary logic. The node leakage current is another problem that has to be handled in deep submicron technology, and new leakage control techniques have to be found to make the dynamic logic circuits continuously attractive.
FIGURE 8.32 A bit-serial pipelined sorter using the compare-and-swap cell.
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