• No results found

A number of possible enhancements to the reduction techniques presented here have been identified throughout the development of this work. They have not been made part of this work because of time constraints. However, are presented in this section in order to show some the possible extensions to these static state space reduction techniques, and which are still unexplored.

• Abstract interpretation. Throughout the definitions of the static analyzes presented in this work, it has been mentioned that no abstract interpretation of the byte-code is performed, thus limiting the scope of the analysis to a purely static approach.

Indeed, an abstract interpretation of the byte-code, including constant propagation and constant folding, may permit more accurate results in these analyzes and cor-respondingly, better state space reductions. For this, it would be useful to create a basic block representation of the control-flow graph as described in [ASU86]. Also, it would be required to apply this analysis to the values of the variables, registers and the operand stack.

• Determination of exclusive access of global variables. Consider a global variable which is used exclusively by one process type. Furthermore, assume that this pro-cess is instantiated only once during the execution of the system. Then, the global variable is really accessed as if it were a local variable of this process. An analysis that is able to detect this situation would allow dead variable reduction to be ap-plied to this variable even in the case of a concurrent system. Likewise, any accesses to this variable need not be considered as external operations when applying path reduction. Thus, both reductions would benefit from this analysis, which would need to determine which global variables are used by which process types, and also, if a given process type may be instantiated multiple times or not.

• Channel analysis. In [MT99], an analysis of Promela is described which determines statically which channel variables may be aliased among each other in any point of the execution of the program. Although this analysis is intended for the slicing of Promela models, the analyzes presented in this work may also benefit from such an analysis, as it offers more precise information about the relationship between channels and variables.

• Elimination of write-only and unused variables. In [Hol99], it is described how Spin detects write-only global variables as well as unused variables and completely re-moves them from the representation of each state. Whereas dead variable reduction causes every variable which is temporarily dead to have a default valuation, this reduction completely eliminates variables which are always dead. Since NIPS is likely to be used as a back-end for compilers, this task will commonly be done by the compiler itself. However, it is possible to implement this optimization directly in NIPS byte-code and thus permit its reuse among all tools which target NIPS.

• Program slicing. A program slicing technique for reducing the size of a Promela model with respect to a given temporal logic specification has been presented in [MT98, MT99]. It is therefore feasible to adapt this same technique to NIPS, which is straightforwardly implementable as a code transformation like the ones presented in this work.

• Partial order reduction. Partial order reduction is the best known state space reduction technique used in software model checking. A mostly-static version of partial order reduction like the one presented in [KLM+98] can be applied to NIPS.

This requires, however, an adaptation of the virtual machine so that it allows the exploration of successor states to be guided by a component that computes the ample sets dynamically, based on statically gathered information.

Thus far, the possibilities for state space reduction in NIPS are very promising, con-sidering the empirical results of this work. The development of future and enhanced

reductions based on the static analysis of NIPS byte-code will support the creation of novel model checking applications which make use of the NIPS virtual machine for the generation of state-transition systems.

Bibliography

[ASU86] Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman. Compilers, Principles, Techniques, and Tools. Addison-Wesley, 1986.

[BFG99] Marius Bozga, Jean-Claude Fernandez, and Lucian Ghirvu. State space re-duction based on live variables analysis. In Agostino Cortesi and Gilberto Fil´e, editors, Static Analysis, volume 1694 of Lecture Notes in Computer Sci-ence, pages 164–178. Springer, 1999.

[CGMP98] Edmund M. Clarke, Orna Grumberg, Marius Minea, and Doron Peled. State space reduction using partial order techniques. Software Tools for Technology Transfer, 2, 1998.

[CGP99] Edmund M. Clarke, Orna Grumberg, and Doron A. Peled. Model Checking.

The MIT Press, Cambridge, Massachusetts, 1999.

[Hol97] Gerard J. Holzmann. The model checker Spin. IEEE Trans. on Software Engineering, 23(5):279–295, May 1997. Special issue on Formal Methods in Software Practice.

[Hol99] Gerard J. Holzmann. The engineering of a model checker: The Gnu i-Protocol case study revisited. In Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking, pages 232–244, London, UK, 1999. Springer-Verlag.

[Hol03] Gerard J. Holzmann. The Spin Model Checker, Primer and Reference Man-ual. Addison-Wesley, Reading, Massachusetts, 2003.

[HP94] Gerard J. Holzmann and Doron Peled. An improvement in formal verification.

In Proc. Formal Description Techniques, FORTE94, pages 197–211, Berne, Switzerland, October 1994. Chapman & Hall.

[IZ93] M. Robert Ito and A. Zaafrani. Data flow analysis for parallel programs.

In CSC ’93: Proceedings of the 1993 ACM conference on Computer science, pages 318–325, New York, NY, USA, 1993. ACM Press.

[KLM+98] Robert P. Kurshan, Vladdimir Levin, Marius Minea, Doron Peled, and H¨usn¨u Yenig¨un. Static partial order reduction. In TACAS ’98: Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems, pages 345–357, London, UK, 1998. Springer-Verlag.

[KLY02] Robert P. Kurshan, Vladimir Levin, and H¨usn¨u Yenig¨un. Compressing tran-sitions for model checking. In CAV, pages 569–581, 2002.

[Lam83] Leslie Lamport. What good is temporal logic? In R. E. A. Mason, editor, Proceedings of the IFIP Congress on Information Processing, pages 657–667, Amsterdam, 1983. North-Holland.

[LC91] Douglas Long and Lori A. Clarke. Data flow analysis of concurrent systems that use the rendezvous model of synchronization. In TAV4: Proceedings of the symposium on Testing, analysis, and verification, pages 21–35, New York, NY, USA, 1991. ACM Press.

[Mil99] Robin Milner. Communicating and mobile systems: the π-calculus. Cam-bridge University Press, New York, NY, USA, 1999.

[MT98] Lynette Millett and Tim Teitelbaum. Slicing promela and its applications to protocol understanding and analysis. In SPIN ’98: 4th International SPIN Workshop, 1998.

[MT99] Lynette I. Millett and Tim Teitelbaum. Channel dependence analysis for slicing promela. In PDSE, pages 52–61, 1999.

[Pel05] Radek Pel´anek. On-the-fly state space reductions. Technical Report FIMU-RS-2005-03, Masaryk University Brno, 2005.

[Roh06] Michael Rohrbach. Model checking embedded systems software. Diploma thesis, Lehrstuhl f¨ur Informatik IXI, RWTH Aachen, Germany, 2006.

[Sch05] Stefan Sch¨urmans. Ein Compiler und eine Virtuelle Maschine zur Zus-tandsraumgenerierung. Diploma thesis, Lehrstuhl f¨ur Informatik II, RWTH Aachen, Germany, 2005.

[TGRW04] Christian Tschudin, Richard Gold, Olof Rensfelt, and Oskar Wibling. LU-NAR: a lightweight underlay network ad-hoc routing protocol and imple-mentation. In NEW2AN ’04: Proceedings of Next Generation Teletraffic and Wired/Wireless Advanced Networking, 2004.

[WPP04] Oskar Wibling, Joachim Parrow, and Arnold Pears. Automatized verifica-tion of ad hoc routing protocols. In FORTE 2004: 24th IFIP WG 6.1 In-ternational Conference on Formal Techniques for Networked and Distributed Systems, volume 3235 of Lecture Notes in Computer Science, pages 343–358.

Springer, 2004.

[WS05] Michael Weber and Stefan Sch¨urmans. A virtual machine for state space generation. Lehrstuhl f¨ur Informatik II, RWTH Aachen, Germany, 2005.

[YG04] Karen Yorav and Orna Grumberg. Static analysis for state-space reductions preserving temporal logics. Formal Methods in System Design, 25(1):67–96, 2004.

[Yor00] Karen Yorav. Exploiting Syntactic Structure for Automatic Verification. PhD thesis, The Technion, Israel Institute of Technology, Haifa, Israel, 2000.