Future work

The work presented in this thesis was an exploratory study on RESURF Si/SiC LDMOSFETs for high temperature operations and will lay a foundation for the succeeding Si/SiC research. The following are some areas that the future work can cover to provide a more in-depth understanding of the Si/SiC architecture.

8.2.1.

Experimental results

In this project, the experimental results are limited to the TEM observations on the Si/SiC interface (see Fig. C.4 in Appendix C). Although the amorphous layer at the interface is very thin (up to 8 nm), its effects on carrier mobility and lifetime are still not clear. To further examine the quality of the Si film on the SiC substrate, experiments such as Hall effects measurements, X-ray diffraction (XRD) [85] and MOSFET fabrication should be performed. These are very important not only to the validation of the FEM models but also the advancement of the Si/SiC study from a conceptual level to a practical solution available for mass production. The works associated with this are currently conducted in the SaSha project, funded by the EU’s Horizon 2020 programme.

8.2.2.

Physical-based TCAD models

In this thesis, all the LDMOS designs were simulated with the same physical-based TCAD models, with differences in the values of the interface charge and carrier lifetime. These settings were used based upon the literature that demonstrated that the fabricated Si/SiC devices had electrical behaviour very similar to the bulk Si and SOI counterparts, and that no adverse effects of the Si/SiC interface had been found on the LDMOS characteristics, for example the reduction of the blocking capability. From a standpoint of analysing the potential of the Si/SiC architecture, this model configuration is reasonable and sufficient enough to deliver credible results for the comparative study. However, it is likely that the wafer bonding and annealing process will degrade the quality of the Si layer and result in a large number of interface charges in the Si/SiC structure. To consider these effects and increase the accuracy, the models are required to be adjusted against the experimental outcomes before being used for device development.

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8.2.3.

RESURF design

In this thesis, the Si/SiC LDMOSFETs were optimised based upon two classic templates—the first using SOI RESURF as in Arnold et al. [46], and the second using PN RESURF as in Disney et al. [99]. These two LDMOS topologies are widely-reported and well-understood, which is helpful to the study and verification of the physical TCAD models. Using these two structures also allows a like-for-like comparison to be made, whereby the effects of the Si/SiC architecture are highlighted. Furthermore, the fabrication techniques of the two LDMOSFETs are mature and can be readily implemented in the Si/SiC for the prototype development. Nevertheless, the Philips and Disney designs were developed and tailored for SOI and bulk wafers respectively, with the consideration of the substrate effects. This means that the electrical characteristics of the Si/SiC devices can be inferior to their SOI and bulk Si references. For instance, the 600 V Si/SiC LDMOSFETs in the SOI technology exhibits a low-side resistance higher than that of the Philips SOI (Chapter 6). As such, it is necessary to apply a RESURF structure more suitable to the Si/SiC architecture for better performance. A 3D RESURF technique can be one option as in this concept, the ideal model features depletion only between alternate n and p-type stripes arranged in the direction of device width [148] [157]. The substrate should not be involved in the development of the space charge regions in the PN pillars. In the traditional SOI and bulk Si structures, substrate assisted depletion is unavoidable and has to be suppressed by some special layouts [101] [157] to achieve charge balancing. This can increase the complexity and cost of the LDMOSFETs. By contrast, the Si/SiC transistor in the 3D RESURF technology does not require those layouts as the (SI) SiC substrate is neutral. A simple example of such Si/SiC design is demonstrated in Appendix B. However, it is worth noting that the Si/SiC interface charge can deplete the n drift region and upset the optimal 3-D field distribution. By using narrower PN stripes, this effect can be reduced due to a higher doping allowance which limits the depletion from the interface. In addition, the presence of a thin oxide layer at the Si/SiC interface can adversely affect the blocking capability. To execute this idea, an experimental work on the Si/SiC interface prior to the simulation is suggested.

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8.2.4.

Switching circuits

In this thesis, the transient simulation was carried out with four different circuits to examine the heating and energy capability of the LDMOSFETs. A common feature of the simulated circuit is that the source of the device is grounded, a typical low-side condition. To deliver high power level, power conversion systems usually employ a half bridge topology where the source of the high-side device is floating [2]. Therefore, to gain a complete picture of the device performance, the high-side switching circuit needs to be simulated. In this case, the transistor can operate in the saturation region where an extreme stress condition is presented [151]. The fast cooling offered by the Si/SiC substrate can protect the device from overheating, thereby increasing the performance and reliability. Additionally, it was found in this work that the Si/SiC LDMOSFETs suffered no degradation in the on-resistance under the high-side configuration, which led to a smaller chip area in a power system.

In a fully-integrated half bridge circuit, the body diode of the LDMOSFET is very important as it prevents the power switch from being energised from the inductive load. This diode will produce losses during the reverse recovery, where significant heating can occur. This effect can be worsened in a hot environment because the reverse recovery time has a positive temperature coefficient [46]. It is expected that the Si/SiC architecture can ensure the safe operation of the diode with the remarkable heat transfer ability. To better understand the diode reverse recovery in Si/SiC devices, TCAD simulation on this should be included in the future work.

It was concluded in Chapter 6 that the Si/SiC architecture could make the LDMOSFETs work more reliably at high frequencies (>1 MHz) due to better heat transfer ability. This was based upon the simulation results of the 600 V Si/SiC and SOI transistor at 200 kHz, in the clamped inductive switching circuit. For a more conclusive study on this topic, it is necessary to simulate the Si/SiC devices at 1 MHz and beyond, under non- isothermal condition

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8.2.5.

LIGBTs

To achieve a higher current in a flyback and half bridge circuit, the low or high-side LDMOSFETs can be replaced with LIGBTs [111] [158]. The LIGBTs in the traditional bulk-Si and SOI technology face problems like slow turn-off [83] and premature punch- through breakdown [158]. The current solutions to this are the membrane bulk-Si and SOI substrate where the substrate effects are eliminated, thereby increasing the speed and blocking capability [83] [158]. In theory, the Si/SiC architecture is well-suited for such bipolar devices as the substrate assisted depletion (SAD) effect is absent in this structure. The lack of this depletion will reduce the doping allowance in the Si/SiC LDMOSFETs, which increases the on-resistance. However, it is expected that less degradation is seen in the Si/SiC LIGBT in the on-state, due to the fact that the resistivity of such device type is determined by minority carrier injection. Furthermore, the (SI) SiC substrate can minimise the heating effect and provide mechanical support during device operation, which is beneficial to harsh environment applications. It is suggested that the research on the Si/SiC LIGBTs should be carried out once the Si/SiC LDMOSFETs are successfully fabricated and tested.

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Appendix…

A

Thermal models

A.1

Methodology

In order to study the heating effect, self-heating model (LAT. TEMP) [122] is activated in the simulation. The lattice heat flow equation is given below [122]:

𝐶𝜕𝑇𝐿

𝜕𝑡 = ∇(𝜅∇𝑇𝐿) + 𝐻 (A.1)

Where 𝐶 is the heat capacitance per unit volume, 𝜅 the thermal conductivity, 𝑇_𝐿 the local lattice temperature and 𝐻 the heat generation. 𝐶 is as the product of specific heat at constant pressure (𝐶_𝑃) and density of the material (𝜌). This equation relates the thermal storage (𝐶𝜕𝑇_𝜕𝑡𝐿) to the thermal transfer (∇(𝜅∇𝑇_𝐿)) and thermal generation (𝐻). A simplified expression for the thermal generation has the form [159]:

𝐻 = 𝐽⃗𝐸⃗⃗ + 𝑈𝐸_𝑔 (A.2) Where 𝐽⃗ is the current density, 𝐸⃗⃗ the electric field, 𝑈 the recombination rate and 𝐸_𝑔 the bandgap of the semiconductor. The first and second term represent Joule and recombination heating respectively. In unipolar devices, the heating mechanism is Joule heating due to the absence of conductivity modulation.

In the steady-state simulation, 𝜕𝑇_𝜕𝑡𝐿 on the left hand side of Equation A.1 is reduced to zero so the lattice temperature is only associated with heat transfer and generation. In the transient simulation, the thermal storage will be significant if the heat capacitance (𝐶) of a material is very large.

To solve the lattice heat flow equation, thermal boundary conditions need to be set in the simulation. In a transistor, all the metal contacts can exchange heat with the ambient

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environment (e.g. package). The substrate contact, however, has the largest area and is connected with the external cooling equipment. This means that the heat escapes mainly via the substrate and hence defining the substrate electrode as the only thermal contact does not dramatically reduce the reliability of the simulation results. For the sake of simplicity, the temperature of the thermal contact is fixed at 300 K or even higher and no external heat sink is specified.

Due to the self-heating effect, the simulated SOI transistors can experience a considerable increase or decrease in temperature. In this case, the temperature effect on the heat capacitance and thermal conductivity are considered to increase the accuracy of the models. This setup was applied by Lim et al. in [5], where the HV LDMOSFETs in PSOI and Philips technology were studied by SILVACO and the authors’ analytic model. A very good agreement was found between the results obtained from the two methods and the thermal advantage of the PSOI device was clearly shown. The following are the settings of the thermal properties for the materials that appear in the LDMOS structure.