Global Timing-driven Placement Techniques

Global timing-driven placement techniques place the entire circuit netlist and redo the placement from the beginning, ignoring the module locations that were obtained from any of the previous stages within a physical synthesis flow. They typically use a net-based approach, where they try to minimize the wire length of the “nets” on the critical paths (also referred to as “critical nets”). The rationale being that optimizing the wire length of the critical nets would implicitly minimize critical path lengths, leading to better critical path delay for the design. To guide the global placement algorithm, these techniques transform the timing constraints or specifications into net specifications, that appear as either net-weights [21, 33, 37, 54, 56, 74], or net-length constraints [24, 29, 51].

To generate reasonably accurate net specifications (net-weights or net-length constraints), these techniques usually follow the physical synthesis flow shown in Figure 6.1. Initially, a

pure wire length driven global placement is performed to obtain some physical information for all the modules in the design. Since the initial placement is timing unaware, this stage is followed by a coarse timing optimization stage, which brings the design to a reasonable electrical and timing state. Based on a timing analysis after the coarse timing optimization stage, net specifications are generated to reflect the timing criticality of the nets in the design. These specifications are used to guide the subsequent timing-driven placement stage, which optimizes the critical nets to improve design timing.

Initial Placement

Coarse Timing Optimization

EP1 EP2 EP3 Clock Insertion and Optimization Detailed Placement and Optimization Fine Timing Optimization

Routing

Post Route Optimization

EP4

Net-weights / Net-length Constraints

Timing-driven Placement Initial Placement

Coarse Timing Optimization

EP1 EP2 EP3 Clock Insertion and Optimization Detailed Placement and Optimization Fine Timing Optimization

Routing

Post Route Optimization

EP4

Net-weights / Net-length Constraints

Timing-driven Placement

Figure 6.1 A physical synthesis flow using net-based timing-driven place- ment. To reflect the timing criticality of the nets, net specifica- tions can be in the form of net-weights or net-length constraints.

The key drawbacks of global timing-driven placement techniques are as follows:

• Global timing-driven placement techniques can result in significant degradation in the total wire length of the design. The reason being, there is no effective method to come up with a good set of net specifications to effectively trade-off total wire length and design timing. Since timing-driven placement minimizes the wire length of the critical nets at the expense of the non-critical nets, inferior net specifications can overly optimize the critical nets leading to a substantial increase in the total wire length. Increase in wire length can also cause severe routing congestion. This is depicted in Figure 6.2 which shows the total wire length and routing congestion at various stages of the physical synthesis flow given in Figure 6.1 on a high performance industrial design. The regions colored pink and purple have more than 100% global routing resource usage - indicating unroutable regions. It can be seen that the global timing-driven placement stage significantly increased total wire length and routing congestion (Figure 6.2 (EP 3)) as compared to the coarse timing optimization stage (Figure 6.2 (EP 2)).

• Global timing-driven placement techniques do not have any interaction with timing op- timization transforms like buffer insertion, gate sizing, etc., for the entire duration of placement. Purely minimizing the critical net wire length without performing any timing optimization in between, will in most cases, degrade the design timing after placement. This is shown in Table 6.1 which gives the design timing at various stages of the physical synthesis flow shown in Figure 6.1 on two of the benchmark designs considered in Section 6.9. As seen from Table 6.1, although the design timing at the end of fine timing opti- mization (EP 4), is better than what is obtained after coarse timing optimization (EP 2), there is a significant degradation at the end of timing-driven placement (EP 3). In addition, a close interaction with timing optimization can potentially re-buffer a net or re-size a gate instead of the corresponding net getting over-optimized during placement at the expense of the other nets in the design. This can potentially lead to significant savings in total wire length, a fact that is demonstrated by the experimental results in Section 6.9.

Stage Steiner Wire Length (×e6) Routing Congestion

EP 1 140.29

EP 2 146.94

EP 3 160.10

Figure 6.2 Total wire length and routing congestion at various stages of the physical synthesis flow given in Figure 6.1. (EP 1) After initial placement (EP 2) After coarse timing optimization (EP 3) After timing-driven placement. (Regions colored pink and purple have more than 100% global routing resource usage).

Table 6.1 Design timing at various stages of the physical synthesis flow shown in Figure 6.1. Although the design timing at the end of fine timing optimization (EP 4), is better than what is obtained after coarse timing optimization (EP 2), there is a significant degradation at the end of timing-driven placement (EP 3).

Evaluation Worst Slack Number of Design

Point (ns) Negative Paths

EP 1 -246.99 21377 EP 2 -0.71 10203 ckt 5 EP 3 -4.03 12110 EP 4 -0.26 2578 EP 1 -976.79 73524 EP 2 -1.14 6610 ckt 8 EP 3 -24.40 24464 EP 4 -0.38 1167

• In addition, net specifications are just an indirect measure of the actual timing con- straints. It is extremely difficult to come up with a good set of net specifications that can effectively optimize design timing within placement.

• For most of the global placement techniques, net specifications are generated at the beginning of timing-driven placement, and are kept constant during the placement stage. This introduces an additional level of inaccuracy. Placement changes can invalidate the timing upon which the net specifications were initially generated. For example, nets that were critical in the beginning could become non-critical very early on during placement. Over-optimizing these nets could cause other non-critical nets to become critical. • Dynamic updation of net specifications during global placement have been proposed (e.g.,

[21, 24, 56]). But in most cases, to maintain placement efficiency, the net specifications are updated using inaccurate timing models. Even if net specifications are updated using accurate timing from a static timing engine, they are based on illegal locations of the modules, as there will be significant module overlap during global placement. In addition, dynamic updation of net specifications during global placement can potentially cause oscillations during placement, resulting in issues with timing convergence.