Intel HDA is a high-fidelity audio bus developed for the consumer market. A detailed de- scription and guidelines for the development of Intel HDA based systems is provided in [22]. Following is a brief summary of the structure of the Intel HD audio link and related compo- nents, as well as data transmission specifics using the HDA bus.
2.5.1
Introduction
There are three key components to any Intel HDA solution: the Intel HD Audio Controller, an Intel HD Audio Link, and one or more Intel HD Audio Codecs, as shown in Figure 2.5. The controller is responsible for communicating audio and control data from the codec to the CPU and memory through a direct memory access (DMA) engine. The bi-directional link is the hardware bus along which audio data and commands are exchanged. The codec sends analog data to physical transducers (i.e. speakers, headphones) and receives analog data from an attached audio device such as a microphone or a line in connection. It is also responsible for digital to analog and analog to digital conversion of the audio data which is communicated along the HDA link.
2.5. IHDA- A 21
Figure 2.6: Intel HDA controller DMA engines[22]
2.5.2
Controller and Bus/Link Description
On system start-up (as well as during forced initialization conditions), the HDA controller is responsible for the discovery and enumeration of all the available codecs on the bus/link. It is responsible for the relay of instructions and data to and from each codec, and it contains the Direct Memory Access (DMA) engines which stream audio data to and from the codec (see Figure 2.6). DMA engines are an efficient method of communicating data between peripheral devices and the system’s memory without having to go through the CPU and usually DMA transfers are faster than non-DMA transfers.
The link itself, which connects a controller with one or more codecs, is a multi-wire electri- cal interface consisting of the BITCLK, SYNCFRAME, and RESET signals. It also contains one to four SDO signals, denotedS DO0−S DO3respectively, which are used to transmit play- back data from memory to the codecs. The SDO lines can be multi-point, i.e. a single SDO line can be attached to multiple codecs. The HDA link contains one to fifteen SDI signals, denoted S DI0−S DIN, which transfer data from the codecs to memory, through the input DMA engines.
Only one SDI line can be associated with a given codec at a time, thus limiting the maximum number of codecs associated to a controller to fifteen.
Figure 2.7: Intel HDA bus signals[22]
SDI line to recover the command response if one is available (command responses for some verbs are not necessary or simply not implemented). Audio data transmission on the SDI lines happens on the raising edge of the clock, unlike the SDO lines, where the data packets are double pumped, i.e. on both raising and falling edges of the clock, thus doubling the effective available bandwidth for playback modes as compared to capture modes using the same audio stream setup. This process is illustrated in Figure 2.7.
2.5.3
Codecs, Nodes and Widgets
An Intel HDA Codec is modular and its design contains a hierarchy of standardized modules. The organization and availability of the internal modules varies between codecs. The codec architecture includes a discovery and addressing scheme that allows for a single driver to easily support a wide variety of codecs, this however only applies a default configuration which is inferred from the current structure of the tree hierarchy of codec nodes and may not match the design intent.
A node is either a single module within a codec or it is a collection of a module and all its children modules that are connected below it in the hierarchy, as shown in Figure 2.8. Each node has a unique address, known as a node ID (NID). An NID is usually 7 bits and has a set of read-only capabilities, and each can be controlled and configured using command verbs
2.5. IHDA- A 23
Figure 2.8: Intel HDA Codec node/widget hierarchy[22]
targeted at that node.
The root node (NID 0x00) is the node at the top of the hierarchy and serves as a pointer to the function groups contained in the codec. Even though the HDA specification does not limit the set of available function groups, currently there are only two supported :modem function group (MFG) or an audio function group (AFG). This thesis is solely concerned with the AFG, as it is the only available function group on the considered HDA codecs.
Within each function group node is a collection of modules known as widget nodes or wid- gets. Widgets can be interconnected different ways, as defined by the codec designer/manufacturer. This allows support of an arbitrary number of audio input and output channels. Widgets are either 1-channel (mono) or 2-channel (stereo). An AFG as a whole can support greater than 2-channel sound by using multiple widgets.
Any widget can be connected to more than one other widget. These hard-wired connections are pre-defined when the codec is designed and are stored in the widget’s connection list. Upon initialization the driver is responsible for interrogating each widget about its connection list. Selection of the required connection is achieved by a command verb targeted at the NID of the widget that contains the list(behaviour inherited from digital multiplexers).
The types of standardized audio widgets are:
• Audio Input Converter (ADC) Widget
• Pin Widget
• Mixer Widget
• Selector Widget
• Power Widget
• Volume Knob Widget
• Beep Generator Widget