The data board is a plug-in board. It provides 9 connectors: the connectors for aperture electrodes, the connector to connect the digital part to the mother board, the connector to connect the analog part to the mother board, the connectors for debugging and the reserved connectors. See Figure 5-9 for the layout of the data board.
See the following table for the function of each connector.
Table 5-46 Interfaces of data board Connector Function Number of
pins Note
J1 Connects the RBC/PLT aperture
electrode 3
/
J2 Connects the WBC aperture electrode 3 / J3 Connects the digital part to the mother
board 96
/
J7 Connects the analog part to the
mother board 96
/
J8 JTAG interface of FPGA 10 /
J9 Reserved 20 /
J10 Reserved 40 /
J11 Reserved 14 /
Figure 5-9 Interfaces layout of data board
Definition of J1
J1 is the signal interface of RBC/PLT.
Table 5-47 Definition of J1
Pin Name Note
1 SHELL Shielding ground
2 RHOLE_A RBC/PLT signals
3 RHOLE_B RBC analog ground
Definition of J2
J2 is the signal interface of WBC.
Pin Definition Function Pin Definition Function
A1 D+5V Power supply B17 JTAG_TCK_ AS
JTAG clock of autoloader board
A2 D+5V Power supply B18 JTAG_TO_A S
JTAG sending of autoloader board
A3 D+5V Power supply B19 JTAG_FROM _AS
JTAG receiving of autoloader board
A4 D+5V Power supply B20 UART1_TO_ DAT+
Reserved debug serial port sending
A5 D+5V Power supply B21 UART1_TO_ DAT-
Reserved debug serial port sending
A6 DGND Signal ground B22 DGND Signal ground A7 DGND Signal ground B23 DGND Signal ground A8 DGND Signal ground B24 DGND Signal ground
A9 DGND Signal ground B25 #VMCTRL Volumetric board enabling A10 DGND Signal ground B26 #RBC_STAR
T
Start RBC volume metering
A11 DGND Signal ground B27 #RBC_STOP Stop RBC volume metering A12 TP_TX+ Positive sending
terminal of network
B28 #WBC_STAR T
Start WBC volume metering
A13 TP_TX- Negative sending terminal of network
B29 #RBC_STOP Stop WBC volume metering
A14 DGND Signal ground B30 DGND Signal ground A15 DGND Signal ground B31 #LASER_CT
RL
Laser board enabling
A16 JTAG_TM S
JTAG mode signal
B32 DGND Signal ground
A17 JTAG_TCK JTAG clock signal C1 D+5V Power supply A18 JTAG_TO_ DRV JTAG sending of drive board C2 D+5V Power supply A19 JTAG_TO_ DAT JTAG receiving of drive board C3 D+5V Power supply
A20 DGND Signal ground C4 D+5V Power supply A21 DGND Signal ground C5 D+5V Power supply
A23 UART0_T O_DAT Serial port receiving of drive board C7 DGND Signal ground
A24 DGND Signal ground C8 DGND Signal ground A25 DGND Signal ground C9 DGND Signal ground A26 DGND Signal ground C10 DGND Signal ground A27 DGND Signal ground C11 DGND Signal ground
A28 DGND Signal ground C12 TP_RX+ Positive receiving terminal of network
A29 DGND Signal ground C13 TP_RX- Negative receiving terminal of network
A30 DGND Signal ground C14 DGND Signal ground A31 DGND Signal ground C15 DGND Signal ground A32 DGND Signal ground C16 UART3_TO_
PC
PC communication serial port sending
B1 D+5V Power supply C17 UART3_TO_ DAT
PC communication serial port receiving
B2 D+5V Power supply C18 DGND Signal ground B3 D+5V Power supply C19 DGND Signal ground B4 D+5V Power supply C20 UART1_TO_
AS+
autoloader board serial port sending
B5 D+5V Power supply C21 UART1_TO_ AS-
autoloader board serial port receiving
B6 DGND Signal ground C22 DGND Signal ground B7 DGND Signal ground C23 DGND Signal ground B8 DGND Signal ground C24 ＃
SUCK_KEY
Aspiration key control input
B9 DGND Signal ground C25 DGND Signal ground B10 DGND Signal ground C26 ＃BUZ Buzzer control output B11 DGND Signal ground C27 #COUNT_KE Aspirate key control input
S_AS autoloader board Y control input
Definition of J7
J7 is the signal interface for the analog part of data board and mother board, and is European 96 pin plug.
Table 5-50 Definition of J7
Pin Name Note Pin Name Note
A1 AGND Analog ground B17 HGB_IN HGB signals input A2 AGND Analog ground B18 AGND Analog ground
A3 AGND Analog ground B19 HGB+ HGB light drive positive electrode
A4 AGND Analog ground B20 HGB- HGB light drive negative electrode
A5 AGND Analog ground B21 A-12V -12V power supply A6 AGND Analog ground B22 A-12V -12V power supply A7 AGND Analog ground B23 A+12V +12V power supply A8 AGND Analog ground B24 A+12V +12V power supply A9 AGND Analog ground B25 A+12V +12V power supply
A10 AGND Analog ground B26 NC /
A11 AGND Analog ground B27 NC /
A12 AGND Analog ground B28 NC /
A13 AGND Analog ground B29 NC /
A14 AGND Analog ground B30 AC120V_ B
Zapping voltage input
A15 AGND Analog ground B31 NC /
A16 AGND Analog ground B32 NC /
A17 AGND Analog ground C1 AGND Analog ground A18 AGND Analog ground C2 AGND Analog ground A19 AGND Analog ground C3 AGND Analog ground A20 AGND Analog ground C4 AGND Analog ground A21 AGND Analog ground C5 AGND Analog ground A22 AGND Analog ground C6 AGND Analog ground A23 AGND Analog ground C7 AGND Analog ground A24 AGND Analog ground C8 AGND Analog ground A25 AGND Analog ground C9 AGND Analog ground
A29 NC / C13 AGND Analog ground
A30 NC / C14 AGND Analog ground
A31 NC / C15 AGND Analog ground
A32 AC120V_ A
Zapping voltage input C16 AGND Analog ground
B1 AGND Analog ground C17 AGND Analog ground B2 LASER_I
N
Laser current monitoring input
C18 AGND Analog ground
B3 AGND Analog ground C19 AGND Analog ground B4 AGND Analog ground C20 AGND Analog ground B5 AGND Analog ground C21 A-12V -12V power supply B6 AGND Analog ground C22 A-12V -12V power supply B7 AGND Analog ground C23 A+12V +12V power supply B8 AGND Analog ground C24 A+12V +12V power supply B9 AGND Analog ground C25 A+12V +12V power supply
B10 AGND Analog ground C26 NC /
B11 FS_IN FS signals input C27 NC /
B12 AGND Analog ground C28 NC /
B13 SS_IN SS signals input C29 NC /
B14 AGND Analog ground C30 NC /
B15 SF_IN SF signals input C31 NC /
B16 AGND Analog ground C32 NC /
Definition of J8
J8 is the JTAG interface of FPGA.
Table 5-51 Definition of J8
Pin Name Note
1 FPGA_TCK Clock
2 GND Signal ground
Reserved. Not available for customers. Definition of J10
Reserved. Not available for customers.. Definition of J11
Reserved. Not available for customers. Definition of J13
J11 is the BDM interface of CPU.
Table 5-52 Definition of J13
Pin Definition Function
1 NC /
2 BKPT# Breakpoint setup
3 GND Signal ground
4 DSCLK synchronizing clock input
5 GND Signal ground
6 TCK Clock input of JATG
7 BDM_RSTI BDM reset
8 DSI Serial input
9 VDD Power supply
10 DSO Serial output
11 GND Signal ground 12 PSTDATA7 13 PSTDATA6 14 PSTDATA5 15 PSTDATA4 16 PSTDATA3 17 PSTDATA2 18 PSTDATA1 19 PSTDATA0 Configuration data 20 GND Signal ground 21 NC / 22 NC / 23 GND Signal ground 24 PSTCLK Processor clock 25 NC /
5.2.3 Adjustment and Test Points
All the adjustable parameters of analog part are adjusted as per the command of FPGA. Adjust the parameters' settings in the software interface if necessary.