Very Large Cells

The algorithms involved in the layout of transistor-level netlists are expo- nential and thus, beyond a certain complexity, do not yield results in an ac- ceptable time frame. Especially when timeouts occur in the first two phases of Algorithm 7, the returned solutions are often very bad. Restricting finger lengths may ease the problem, but some cells are even too large for the easiest parameter configurations.

For this reason, BONNCELLincludes a mode designed to handle very large

cells. In this mode, optimality is sacrificed in favor of a fast computation of heuristic arrangements. A top-level description is given in Algorithm 8. The idea is to split the complex netlist into several less complex netlists, process each of them individually, and finally concatenate the computed layouts. The flow is visualized in Figure 5.6.

Number of Subcells

One input parameter of the algorithm is the number of subcells into which the large instance should be split. This number k is determined automatically based on various measurements of the exact algorithm’s performance. In the current implementation, the number k is chosen such that the average number of FETs per subcell is at most 10 and the average sum of gate lengths is at most 80 per subcell.

Target Function

Previously, the gate netlength has been a much more important value than the total netlength. This decision was motivated by the desire to realize con- nections between the gates on the PC and M0 layers as compact as possible. However, other challenges become prevalent on very large cells.

One can observe that most of such cells contain so many long horizontal con- nections that, using the normal placement engine, some x-coordinates have to be passed by too many different nets for the cell to be routable. Hence, it is more important to reduce the horizontal cut, i.e. the largest number of nets

Algorithm 8: BigCellPlacement Data: A netlistF, a number k

Output: A 2-dimensional layoutΛ

1 if pins are defined near the left and right cell borders then 2 Place FETs with such pins near the cell’s border

3 Compute positions for other FETs by an iterative mean heuristic 4 else

5 Compute rough placement using a linear arrangement heuristic 6 Split netlist into k smaller instances based on rough placement 7 Apply CellPlacement to every sub-instance

8 return Concatenation of the k layouts

that have to cross any given x-coordinate, as much as possible. On complex cells, we therefore do not give the gate netlength any priority as we did in the definition of the layout quality Q.

Rough Placement

In order to find a reasonable cut at which the netlist is split, a rough place- ment is determined in lines 1 to 5, using one of two methods. These methods neither produce legal layouts nor determine swap statuses or finger num- bers, their purpose is merely to generate horizontal locations for each FET. If the instance contains for both the left and the right cell border at least one net with a pin defined near that border, then a heuristic is applied that takes advantage of those pins. This is the case for most of the cells in practice, as input pins are usually assigned to the left cell border and output pins to the right cell border. The first step is to place the FETs that are connected to such nets very far apart. For FETs with a connection to the left border, x(F)is set

to 0, for FETs connected to the right cell border, it is set to 100k. All remaining FETs are initially placed at the coordinate 50k.

Thereafter, all locations are updated in 10 iterations. In each iteration, the new x-coordinate for a FET F is determined as the weighted average of the FETs connected to F through at least one net. Net weights are used as weights in the computation. Gate connections are not prioritized over source or drain connections for the reason given above. After new coordinates have been assigned to all FETs, the arrangement is stretched to the interval[0, 100k]in

order to prevent all FETs from collapsing to a single point. In particular, xmin:=minF∈Fx(F)and xmax:=maxF∈Fx(F)are computed and then

x(F) ← x(F) −xmin

xmax−xmin ·100k

5.2. CELLS WITH TWO FET ROWS 85

Subcell 1 Subcell 2 Subcell 3

(a) Rough placement heuristic and induced assignment of FETs to subcells

(b) Optimal layout for every subcell

(c) Resulting large cell layout Figure 5.6: Illustration of Algorithm 8.

If the pin definitions do not induce a reasonable initial assignment of vary- ing x-coordinates, a heuristic developed to solve the MINIMUMLINEAR AR- RANGEMENT problem is applied instead. In this case, we define a graph

G= (F ∪ {vl, vr}, E)in which two FETs are adjacent if a net exists that con-

nects these two FETs. The two special vertices vland vrrepresent the left and

right cell borders and are adjacent to all FETs which are connected to a net on which a corresponding pin is defined. Note that the method is only applied when vlor vris an isolated vertex.

After the graph has been constructed, the method proposed by Pantrigo et al. [PDCM11] is applied, which is an extension of the earlier heuristic by McAllister [McA99]. Algorithm C3 from [PDCM11] is used as a subroutine with β set to 0.5. The method is modified such that vl is the first vertex to be

labeled and vris the last vertex labeled during the algorithm. When a label

l(F)has been assigned to all FETs, those values are taken as x-coordinates of

the rough placement in line 5 of Algorithm 8.

Splitting the Netlist

The x-coordinates of the rough placement induce a total order≤on the set of FETs. If two FETs F1 and F2have the same location in the rough placement,

connected to the gate of Fi. This tie-breaking criterion favors assignments in

which FETs with the same gate net are contained within the same subcell. We number the FETs F1, . . . , Fnsuch that F1 ≤. . .≤ Fn.

Then indices n1, . . . , nk−1 are chosen and the sets Fi := {Fni−1+1, . . . , Fni}, where n0 := 0 and nk := n, are defined as the transistor sets for the sub-

cells. The numbers are chosen such that

k

∑

∑

∑

is minimized, i.e. the sum of deviations from the average FET area. The in- stances are small enough so that n1, . . . , nk−1 can be determined by enumer-

ating allO(nk−1)possibilities.

Finally, the nets in subcell i are exactly the nets connected to FETs inF_i. How-

ever, if a net N in subcell i is connected to some FET inF₁∪. . .∪ F_i−1, then a pin is defined on the left border of the subcell, i.e. pN

x,rel =0, to model the con-

nection to the left. Analogously, a pin on the right subcell border is defined if a net is connected to another subcell further to the right.

Placing the Subcells

When the subcells have been constructed, Algorithm 7 is invoked on each of them individually. As the reduced instances are relatively small, this usually results in optimal layouts in a short runtime. These layouts are concatenated with sufficiently large spacing between them so that no design rules are vio- lated. Figure 5.6 illustrates this method.