8.2.1.2 8B10B Encoding/Decoding

8.6 Auto-Negotiation and Link Setup 2

8.6.1 Link Configuration in Internal Serdes/TBI Mode 1

Internal Serdes for the 82546GB/EB and 82545GM/EM (TBI for the 82544GC/EI) Mode link configuration can be performed via the on-chip PCS function in the Ethernet controller. The hardware supports both hardware and software Auto-Negotiation methods for determining the link configuration, as well as allowing for manual configuration to force the link.

Hardware Auto-Negotiation is the preferred method.

8.6.1.1 Link Speed

Internal Serdes for the 82546GB/EB and 82545GM/EM (TBI for the 82544GC/EI) Mode is only defined for 1000 Mb/s operation. Other link speeds are not supported.

When the 82546GB/EB and 82545GM/EM is in internal Serdes mode, the speed determination function is disabled and the Device Status register bits (STATUS.SPEED) bits indicate a value of 10b for 1000 Mb/s.

For the 82544GC/EI, when the TBI_MODE input is asserted for TBI mode, the speed determination function is disabled and the Device Status register bits (STATUS.SPEED) bits indicate a value of 10b for 1000 Mb/s.

8.6.1.2 Auto-Negotiation

At power up, or Ethernet controller reset via the RST# input, it initiates Auto-Negotiation based on the default settings in the Device Control and Transmit Configuration Word registers, as well as settings read from the EEPROM. If enabled in the EEPROM, the Ethernet controller immediately performs Auto-Negotiation.

TBI Mode Auto-Negotiation, as defined in clause 37 of the IEEE 802.3z standard, provides a protocol for two Ethernet controllers to advertise and negotiate a common operational mode across a Gigabit Ethernet link. The Ethernet controller fully supports the IEEE 802.3z Auto-Negotiation function when using the internal Serdes mode for the 82546GB/EB and 82545GM/EM or when using the TBI and on-chip PCS for the 82544GC/EI.

TBI Mode Auto-Negotiation is used to determine the following information:

Duplex resolution

Flow control configuration

Speed for Internal Serdes mode (TBI mode for the 82544GC/EI) is fixed at 1000 Mb/s, so speed settings in the Device Control register are unaffected by the Auto-Negotiation process.

There are two implementations accessible in the design:

1. A full hardware Auto-Negotiation implementation that does not require software intervention in order to successfully reach a negotiated link configuration.

2. Software driven negotiation.

1. TBI mode for the 82544GC/EI.

A set of registers is provided to facilitate either hardware or software Auto-Negotiation.

The hardware supports both hardware and software Auto-Negotiation methods for determining link configuration as well as allowing for manual configuration to force the link. The IEEE 802.3z specification defines a set of resources that software can use to control a hardware implementation of Auto-Negotiation, but this definition is sub-optimal for Internal Serdes mode (TBI mode for the 82544GC/EI) and hardware Auto-Negotiation is the preferred method.

In addition, it specifies optional resources that exist only to support the exchange of “Next Pages”, something that is not required for the Ethernet controller. The hardware defined in this

specification accepts and exchanges next pages in Internal Serdes mode (TBI mode for the 82544GC/EI), but does so by dropping all incoming next pages and sending only null next pages.

The Ethernet controller can only send null next pages when in hardware Auto-Negotiation. A full next page exchange can take place if software performs Auto-Negotiation.

The Ethernet controller fully complies with IEEE 802.3z with respect to next page exchange in that both link partners must request next page exchange in order to do so.

8.6.1.3 Hardware Auto-Negotiation

Hardware supports negotiation of the link configuration per clause 37 of the 802.3z standard. This is accomplished by the exchange of /C/ ordered sets that contain the txConfigWord register values from TXCW in the third and fourth symbols of the ordered sets.

Bits FD and LU of the Device Status register (STATUS), and ANC of the RXCW register provide status information regarding the negotiated link.

Auto-Negotiation can be initiated by the following:

LRST transition from 1b to 0b in CTRL register

ANE transition from 0b to 1b in TXCW register

Receipt of /C/ ordered set during normal operation

Receipt of different value of the /C/ ordered set during the negotiation process

Transition from loss of synchronization to synchronized state (if ANE is enabled) Resolution of the negotiated link determines device operation with respect to flow control capability and duplex settings. These negotiated capabilities override advertised and S/W controlled device configuration.

Figure 8-3. 802.3z Advertised Base Page Mapping Table 8-2. Bits Content in TXCW.txConfigWord

The reserved bits should be written as zero. The remote fault bits [13:12] can be set by software to indicate remote fault type to the link partner if desired. The AS and PS bits are used for

advertisement of PAUSE frame operation. Refer to clause 37 of the 802.3z specification for details.

8.6.1.4 Software Auto-Negotiation

Auto-Negotiation can also be performed by software with TXCW.ANE set to 0b. Data stored in the txConfigWord field is transmitted during the configuration process. Software should not (in general) read back the contents of this register.

If hardware loses receive synchronization, the contents of the TXCW register changes and during the time of the change, the value read back can be inconsistent. In the absence of loss of

synchronization, the value read back is stable and equal to the last written value.

Software controls the negotiation process by writing the appropriate values to the txConfigWord and transmitting /C/ ordered sets by setting txConfig (in TXCW) to 1b. Software must monitor the RXCW register for status of the negotiation process and respond via writes to the TXCW register appropriately.

The software algorithm must follow the state machine implementation of sub-clause 37.3.1.5 of IEEE 802.3z, Figure 37-6. The link timer specification is 10 ms (+10 ms/-0 ms). In some systems, response time for the S/W implementation can make it difficult to meet this requirement if system utilization is high due to latencies on the PCI bus.

For more information, refer to the register definitions for TXCW and RXCW in Sections 13.4.13 and 13.4.14, respectively.

Bit Description

Np Next Page Indication

When set indicates a request for next page exchange

AS

Asymmetric Pause Connection is Desired

When set, results in independent enabling/disabling of the flow control receive and transmit. When cleared, results in symmetric enabling/disabling of the flow control receive and transmit

PS

Pause Function

When set, indicates that the Ethernet controller is capable and intends to stop upon reception of 802.3x flow control Pause packets.

When cleared, indicates that the Ethernet controller is not capable, or does not intend to stop upon reception of flow control Pause packets.

HD

Half-Duplex Ability

When set, indicates that the Ethernet controller is capable of working in half-duplex mode of operation

FD

Full Duplex Ability

When set, indicates that the Ethernet controller is capable of working in full-duplex mode of operation

RSV Reserved

Should be written as 0b

8.6.1.5 Forcing Link

In cases where the Ethernet controller is connected to a non-Auto-Negotiating link partner, the hardware allows for manual configuration of the link via the Device Control register (CTRL).

Forcing link can be accomplished by software writing a 1b to CTRL.SLU which forces the TBI PCS logic into a link up state if the LOS input is not asserted. Setting the SLU bit enables the MAC to communicate with the internal SerDes and allows recognition of the LOS signal. If auto-negotiation is enabled (TXCW.ANE = 1b) Set Link Up is ignored. The LINK UP# output, as well as internal status logic, indicates link status.

The TXCW.ANE bit must be set to logic 0b to allow for forcing link. When link is forced via the CTRL.SLU bit, the link cannot come up unless the LOS input is deasserted, implying there is a valid signal being received by the optics or the SerDes.

An interrupt bit, RXCFG, flags software that the hardware is receiving configuration symbols (/C/

codes). Software should mask (enable) this interrupt when forcing link. When the link is forced, the link partner can begin to Auto-Negotiate based due to a reset or enabling of Auto-Negotiation. The reception of /C/ codes causes an interrupt to software and the proper hardware configuration can be set.

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