LOCAL AREA NETWORK I/O LAYOUT - Bypass capacitors between controller and data line filter

Trace Width

Technique 2. Bypass capacitors between controller and data line filter

5.4 LOCAL AREA NETWORK I/O LAYOUT

Local area networks (LANs) and wide area networks (WANs) require

careful attention during layout to allow compliance to international interface and emission requirements. The most commonly used LANs are Ethernet, Token Ring, FDDI (Fibre Distributed Data Interface), Wireless and

Broadband. A sample listing of these specifications includes

Ethernet has different interface formats, each with a different front-end connector and design considerations. The most widely used Ethernet protocols are listed here. This list is not intended to be comprehensive, but only to illustrate variations within one type of LAN: Ethernet.

Telecommunication circuits also have various formats, each with a unique interface requirement. A sample listing includes T1, ISDN, D3, OC3, E1, E3, and the like.

The recommended design implementation for typical interconnects is illustrated in Figs. 5.9 to 5.12, which show a number of similarities. The layout concept and implementation merit close observation. Specific design details are left to the designer and will differ based on specific

implementation requirements for each application. Typically, the order of component layout from the controller is: isolation transformer/wave shaping

ISO/IEC

8802.3 Carrier Sense Multiple Access with Collision

Detection (CSMA/CD) Access Method and Physical Layer Specifications (Ethernet).

ISO/IEC 8802.5

Token Ring Access Method and Physical Layer Specifications. Subsections include STP (Shielded Twisted Pair), UTP (Unshielded Twisted Pair), and Fiber Optic.

ANSI X3.166

Fibre Data Distributed Interface (FDDI)—Token Ring Physical Layer Medium Dependent (PMD).

1. 10Base-10, 10Base-5

(10/5 MHz, AUI—Coax) 2. 10Base-2 (10 MHz, Thinnet—Coax)

3. 10Base-T (10 MHz, RJ-45—twisted pair, shielded or unshielded)

4. 10Base-F (10 MHz, FOIRL—Fiber Optic) 5. 10Base-FL (10 MHz, FL—Fiber Optic)

6. 100Base-TX (100 MHz, 100Base-T using two pairs of Category 5 UTP cable)

7. 100Base-T4 (100 MHz, 100Base-T using four pairs of Category 3, 4, or 5 UTP cable)

100VG-AnyLAN (100 MHz, using Category 3, 4, or 5 UTP, STP cable and fiber optic)

9. Gigabit

Ethernet (Copper or fiber optics)

circuit, data line filter, and I/O connector.

Figure 5.9: Suggested layout for network and telecommunication

interfaces.

Figure 5.10: Suggested layout for coaxial based

interconnects.

Figure 5.11: Suggested layout for fiber optic

interconnects.

Figure 5.12: Suggested layout for a sophisticated fiber

interface.

The recommended layout topology shown in Figs. 5.9 through 5.12 has been proven to allow compliance with International Class B emission requirements. Proper design of the interface is not the total solution for electromagnetic interference compliance. All other areas discussed in this book are still required, especially trace routing, proper selection of

components and their placement, correct I/O isolation and filtering, optimal decoupling, and other design and layout techniques.

Personal account | University of Southern Queensland

Search: All Content All Collections

Content Browse Tools: Plus text Tips

Table of Contents

5.4: LOCAL AREA NETWORK I/O LAYOUT

5.5: VIDEO 5.6: AUDIO REFERENCES

Chapter 5 - Interconnects and I/O

Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition by Mark I. Montrose

5.5 VIDEO

Printed circuit boards with video require careful attention to impedance control, filtering, and grounding. For analog monitors, the slowest slew rate signal possible from the video generator is required. A passive filter must be installed between the video generator and I/O connector. Locate the filter immediately adjacent to the connector with minimal lead inductance.

Manufacturers of video controllers generally prescribe a recommended way to layout the design, including selection of discrete components. For analog monitors, maintain constant trace impedance of the three RGB signals (red, green, and blue), along with both horizontal and vertical sync traces. These layout requirements prevent reflections from being

developed owing to a potential transmission line impedance mismatch in the system and interconnect cable.

Two major concerns exist when performing a video layout: trace impedance and power purity. Trace impedance between the video generator and I/O connector must be matched to the video monitor for optimal performance. A typical PCB has trace impedance in the range of 55 to 65 ohms. Video requires 75 ohms, hence, an impedance mismatch will be present if a standard line width is used. For very dense, multilayer PCB assemblies, trace routing must occur over an area identified as an absence of copper section directly under the 75 ohm RGB circuitry to alter trace impedance of specific signals. This absence of the copper area

(plane) forces the signal traces to be impedance referenced to a plane at a greater distance away, increasing overall impedance. This absence of copper area also prevents digital power plane noise from corrupting low-voltage level analog signals. A design technique to maintain impedance control is to alter the physical width of the trace on each routing layer in order to maintain a desired impedance throughout the trace route.

Referencing a trace to a plane at a distance farther away within the

stackup is how one can route a trace with a different impedance value than other traces with the same width on the same routing layer (Fig. 5.13).

Figure 5.13: Routing 75-ohm traces on a 50-ohm stackup

assembly.

Most video systems require 75 ohm impedance. This higher impedance is required only from the output of the video generator to the I/O connector.

Thus, the distance spacing of the routing layer to the reference plane between the controller and connector must be at a constant 75 ohm impedance for all analog traces within this area. Altering the width of the trace may also be required when the trace has to traverse through a via to another routing plane, which itself has a different impedance value. A trace width change is applicable when a signal layer is referenced to an alternate image plane. (Impedance control of microstrip and stripline layers is

discussed in Chapter 4.)

One must maintain constant trace impedance for video signals routed on all layers from controller to connector. If this trace is routed 100% in the same signal plane, adjacent to a solid reference plane (tightly coupled), design techniques for alternating the trace width for each routing layer of the PCB for impedance control are not required.

With regard to power purity, a filtered isolated power source referenced to noisy (digital) power through a ferrite bead is required. Adequate

decoupling must also be present for both the digital and analog side of the ferrite bead. A second ferrite bead for analog ground may be required (discussed next). All video and analog traces and their respective components must be located exclusively in the analog section. Proper component placement prevents digital switching noise from corrupting analog components. When designing isolation for analog with a moat between analog and digital, the 20-H rule is required only for the analog power plane, shown in Fig. 5.14.

Figure 5.14: Video circuitry layout concept.

If the vendor ties analog ground to digital ground internal to the device package and instructs the user to tie analog ground to the digital partition externally, then why has the vendor allocated the pin name as AGND? In reality, only one ground structure exists. The moat for the analog section needs to be routed to those components using filtered "analog" power. "All"

video traces must be routed within the analog section, and their respective RF return currents must remain in analog, not digital. If the analog traces are routed over a digital plane, digital switching noise may couple to the analog traces (crosstalk), causing signal integrity concerns.

One must not violate or cross the moat with the placement of "any"

component or trace that physically resides exclusively in either the digital or analog section. Use of the 20-H rule assists in implementing this

technique. It is recommended that the surrounding planes be at ground reference rather than voltage to minimize crosstalk between traces. This is shown in Fig. 5.14 for a multilayer stackup. For two-sided boards, the same

Note Certain vendors of video controller RAMDACs (random access memory digital-to-analog controller) tie analog ground to digital ground internal to the device package. This connection may also be performed internal to the silicon die. If the RAMDAC chosen has these two grounds connected internally together, then it is imperative that a solid ground plane be used for both analog ground and digital ground. A ferrite bead for ground pins should not be used with this particular type of RAMDAC. Other vendors have RAMDACs designed with pure isolation between analog ground and digital ground through CCD (Charged Coupled

Devices) internal to the device package. For these parts, a ferrite bead for ground is mandatory.

guidelines apply but with extra attention given to component placement and trace routing to prevent coupling noise between analog and digital sections. The discrete video filter components must always be located adjacent to the I/O connector, with minimal trace length routing possible.

Certain analog monitors use a coax from the I/O connector to the monitor.

The braid, or shield, of the coax is not an RF shield but a video signal return path. This braid (shield) therefore cannot be RF bonded to chassis ground; rather it must be connected directly to the video return logic.

Provision must always be made for an AC shunt using a bypass capacitor between the braid (shield) of the coax and system chassis ground. The shunt capacitor removes RF currents that may exist on the coax shield without affecting the signal integrity of the transmitted signal.

RF energy on a braid travels on the basis of skin effect. The inside portion of the braid carries the video return signal, whereas the outside portion of the braid carries RF energy. Because of the propagation mode of the electromagnetic wave within a transmission line, both RF and low-frequency energy will be present simultaneously. For this reason, the bypass capacitor is effective in removing unwanted high-frequency RF energy, while letting the desired low-frequency DC signal to pass undisturbed.

For PCBs with digital mode video interface, data line filters, or their equivalent, must be used only on high-threat signals. Constant trace impedance is mandatory at all times, taking into consideration layer jumping. The output portion of the video generator to the I/O connector must be located in an isolated (quiet) area (discussed earlier). RF ground (bond) the metal I/O connector and cable shield directly to chassis ground immediately at the exit point, if the cable braid (shield) is not used as signal return. If the I/O connector contains video return, then design requirements mandate isolation. Under this condition, a bypass capacitor is required to divert RF energy on the braid to chassis ground. Externally induced RF energy is not to be allowed to corrupt the video circuitry once it enters the system.

Use of content on this site is expressly subject to the restrictions set forth in the Membership Agreement.

Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.

Personal account | University of Southern Queensland

Search: All Content All Collections

Content Browse Tools: Plus text Tips

Table of Contents Chapter 5 OVERVIEW 5.1: PARTITIONING 5.2: ISOLATION AND PARTITIONING (MOATING) 5.3: FILTERING AND GROUNDING

5.4: LOCAL AREA NETWORK I/O LAYOUT

5.5: VIDEO 5.6: AUDIO REFERENCES

Chapter 5 - Interconnects and I/O

Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition by Mark I. Montrose

5.6 AUDIO

Printed circuit boards with audio generally require three separate

partitioned areas: digital, analog, and audio. This multilevel partitioning is applicable only for a four- or more layer stackup, and it is impossible for two-layer assemblies. Most two-layer PCBs do not implement moats, for it is impossible to use split plane technology when solid reference planes do not, and cannot, exist.

The analog section must be isolated from the digital area using a bridge or moat. An example of this multilevel partitioning is shown in Fig. 5.15. The concept used for partitioning analog and digital is similar to a video layout, discussed in the previous section.

Figure 5.15: Audio circuitry layout concept.

When designing a moat structure for analog power and ground, route traces between the digital and analog section in the area immediately adjacent, or under the audio controller, using a ferrite bead between analog/digital power and ground. If a common ground plane is used for both analog and digital components, only the power plane needs to be moated (isolated). The 20-H rule should be used only on the analog power plane (Fig. 5.15).

Depending on how the audio controller is partitioned, analog ground and digital ground may be connected together. If the controller requires a full partitioned analog ground from digital ground, a ferrite bead becomes mandatory. Sometimes only the power plane is moated. If a multilayer assembly is not provided, a trace must be used, also filtered.

All interconnect traces not associated with the audio controller must traverse through a bridge located directly under the audio controller and physically adjacent to a solid reference (image) plane. Violation of any trace over the moat, not traveling through the bridge, separating the analog to digital partition, will allow digital switching noise, white noise, and other

electrical disturbance to be injected from the digital section into the analog section. White noise is random noise that has a constant energy per unit bandwidth throughout the frequency spectrum. Power supply and system noise is usually heard as a 50/60 cycle hum and is not classified as white noise.

The audio interface must be treated differently from both the digital logic and analog control section. To prevent chassis switching noise from

coupling to the audio I/O cables, complete isolation of the digital power and ground planes is mandatory. An audio cable usually consists of a two-wire pair: signal and return for each channel. If this type of two-wire cabling is used, the audio I/O interface connector must be isolated from the rest of the PCB using a moat.

Data line filters must be used to remove common-mode currents injected into the audio section from the external cable, as well as providing isolation from an ESD event or RF-induced energy onto the interconnect. In

addition, a second set of data line filters between the analog section and audio interface should be provided. Do not incorporate a ground choke or inductor to reference "analog" ground to "audio" ground. A ground choke, or inductor, places inductance into the ground circuit. This

inductance causes the transference of board-induced noise voltage to be passed from a noisy part of the PCB into a quiet or clean audio section.

The filter circuit must be placed directly at the point of entry.

Analog traces and components must be located within the isolated analog section. This placement prevents coupling between the digital section to analog. This partitioning is illustrated by a "dead zone" on Layer 3 in Fig.

5.15. Use of the 20-H rule may also be required in the analog section of the PCB. It is preferred that the surrounding reference planes be at ground potential rather than power in order to minimize crosstalk or digital switching noise that may exist within the planes.

If using a cable with a RF braid (similar to a shielded two-pair

instrumentation cable), a bypass capacitor (typically 0.01 ˤF) is used to connect the braid of the audio cable directly to chassis ground. Thus, the braid, or mylar foil shield of the cable will be signal return, not RF ground or RF shield. Bypass capacitors remove high-frequency RF energy from

corrupting audio quality while allowing compliance with EMI requirements.

Different vendors of peripheral devices such as speakers and joysticks do not terminate the braid of the interconnect cable.

Use of content on this site is expressly subject to the restrictions set forth in the Membership Agreement.

Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.

Personal account | University of Southern Queensland

Search: All Content All Collections

Content Browse Tools: Plus text Tips

Table of Contents Chapter 5 OVERVIEW 5.1: PARTITIONING 5.2: ISOLATION AND PARTITIONING (MOATING) 5.3: FILTERING AND GROUNDING

5.4: LOCAL AREA NETWORK I/O LAYOUT

5.5: VIDEO 5.6: AUDIO REFERENCES

Chapter 5 - Interconnects and I/O

Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition by Mark I. Montrose

REFERENCES

[1] Montrose, Mark I. 1999. EMC and the Printed Circuit Board—Design, Theory and Layout Made Simple, Piscataway, NJ: IEEE Press.

[2] Drewniak, J. L., T. H. Hubing, and T. P. Van Doren. 1994.

"Investigation of Fundamental Mechanisms of Common-Mode Radiation from Printed Circuit Boards with Attached Cables." Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, pp.

110–115.

Use of content on this site is expressly subject to the restrictions set forth in the Membership Agreement.

Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.

Personal account | University of Southern Queensland

Search: All Content All Collections

Content Browse Tools: Plus text Tips

Table of Contents Chapter 6 6.1: INTRODUCTION 6.2: TRIBOELECTRIC SERIES 6.3: FAILURE MODES FROM AN ESD EVENT

Chapter 6 - Electrostatic Discharge Protection

Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition by Mark I. Montrose

Chapter 6: Electrostatic Discharge

In document Printed Circuit Board Design Techniques for EMC Compliance_A Handbook for Designers, Second Edition (Page 178-186)