Main controller

The global system, which includes the validation platform and the image processing algorithms, is composed by several modules, as presented in Figure 3.7. To manage these modules, a main controller, named here as “ControlImig”, was implemented.

The interaction between the Control Imig and the other modules is mainly supported by a 4-phase handshake protocol. This protocol is not related with message communication, but it is related with synchronization between the modules. It is a 4-phase handshake protocol that uses pairs of Request/Acknowledge signals [47]. Using this protocol, the transmitter component makes a request to another component, setting the Request line. The receiver (other component) receives the request and sends back an acknowledge (setting the Acknowledge line). When the acknowledge is received, the transmitter component stops making the request, resetting the Request. But it waits until the receiver component ends, which is signalled with the Acknowledge reset. So, this way the components are synched with each other and the transmitter only makes another request after the receiver ends.

This protocol is used to control/synchronize operations such as read from the DDR2, write, apply image processing, control how information comes and goes to UART, and more. It has control over all components and communicates with them by making requests and expecting

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acknowledges to those requests. In Table 3.4 is shown the main actions controller by the ControlImig flow.

Table 3.4: Main operations controlled by ControlImig.

Name Description

Initialize DDR2 positions Initializes the DDR2 positions value with 0. Receive image from UART The PC sends and image via UART to the

FPGA.

Write image in DDR2 An image is stored in the DDR2. Read image from the DDR2 Retrieves an image form the DDR2.

Algorithms Applies the algorithms to the image stored in the DDR2.

Read data from DDR2 to UART Reads data from the DDR2 and sends it to the PC via UART.

ControlImig has 3 main processes running simultaneously. It has the Main process, where all the requests for certain operations are made, the Write process, where all the write operations are controlled, and the Read process, where all the read operations are controlled.

The first operation controlled by Control Imig is the “Initialize DDR2 positions”. It consists in initializing the DDR2. The DDR2 initialization command is issued, but its memory positions come with a default value different from zero. Since the image and the data are stored in the DDR2, those positions should to be initialized to zero to ensure data integrity.

The second operation that the Control Imig is responsible for, is “Receive image from UART”. Having the DDR2 initialized and with its memory position values cleared, the system is ready to receive an image. The transmission of the image to the FPGA is made through data exchange through the UART.

The next operation (“Write image in DDR2”) consists in writing the image data in the DDR2. Since the DDR2 allows writing a maximum 128 bits in a write operation, 128 bits of data image are fetched and stored.

Control Imig also controls the “Read image from the DDR2” operation, which fetches 128 bits per read operation from the DDR2. Whenever image data is read, Control Imig executes the operation “Algorithms”. This operation consists in applying the developed image processing algorithms and store their result in the DDR2. One of those algorithms, which saves a matrix in the DDR2, is described in detail on Chapter 4.

The last operation Control Imig performs is to send the stored information in the DDR2 back to the computer. This is achievable trough the UART module.

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3.4.5 Main File

The Main file instantiate all the modules and is responsible to interconnect their inputs and outputs and the global system inputs and outputs. It is implemented as the top module of the Xilinx project. The connections between modules could be done via schematic, but since the quantity of modules and connections are quite big, it was chosen to do it in VHDL. The connections are made by defining each module with its own port map, which maps signals in an architecture to ports on an instance within that architecture. To deploy the code to the FPGA, Xilinx ISE uses the tool Impact to load a .bit file to the FPGA. Since the bit file generated is the top module file, the file loaded into the FPGA is the main.bit file. The next sub section explains what the UCF file is and how it relates to the main file.

3.4.6 UCF File

The User Constraints File (UCF) file is dedicated to connecting the inputs and outputs to the FPGA pins, to constrain clocks, paths, and more. The inputs connected to the board push buttons were 3, an input to make the initial reset, an input to init the DDR2 and an input to start the program flow.

The next section provides a detailed description about the application developed in C# to perform the pre-processing task and to compare the output of the FPGA with the initial input.