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7-2. THE MASTER TRIP CIRCUIT AND THE PROTECTION CORE

In document 2b - GEH-6353B MK 5 LM Panel Manual (Page 109-113)

APPLICATION SPECIFIC FUNCTIONS

7-2. THE MASTER TRIP CIRCUIT AND THE PROTECTION CORE

Turbine protection in the Mark V LM Control System is performed by multiple cores within the control panel. The following text and illustrations show the manner in which various protective functions are implemented.

There are two parts to the Master Trip Circuit: the inputs to the Mark V LM and the outputs from the Mark V LM.

The "hardwired" or remote trip inputs to the Mark V LM (contact open to trip) connect to the "4’s" relay coils (known as the "4’s"

for the ANSI standard device number referring to the Master Protective). These relays are energized during normal operation by 125 V dc from the power distribution core. This circuit has redundant relay coils connected to the positive dc bus in series with the external trip contact inputs and another set of redundant relay coils connected to the negative dc bus. (See Figure D-45.) A failure of any one of the four "4’s" relay coils will not accidentally trip the turbine. Only de-energizing both relays connected to the same (positive or negative) dc bus will trip the turbine.

If an external trip signal is received, the "4’s" trip circuit will de-energize and the voting contacts circuit will de-energize the internal 24 V dc protective bus. The supply to this 24 V dc protective bus comes from a circuit which selects the maximum voltage from three power supplies; one on each TCEA board in the <P1> core.

The 24 V dc protective bus supplies all the primary trip relays (PTRs), emergency trip relays (ETRs), and other relays which interface with the turbine trip solenoids. These PTR’s and ETR’s comprise the output portion of the Master Trip Circuit. The microprocessors on the TCEA boards monitor the status of the "hardwired" or remote trip inputs, however, the actual tripping is independent of any microprocessor.

The PTR's, ETR's, and “4’s” are located on the TCTG board.

The Control Sequence Program (CSP) located in the <R> processor, provides protection for conditions such as loss of flame, starting means failure, excessive exhaust temperature spreads, excessive vibration, over temperatures, primary overspeed trip, and loss of hydraulic oil via the PTRs of the Master Trip Circuit. The PTR trips are JOB SPECIFIC and are defined in the CSP.

The <P1> core consists of three independent, identical TCEA printed circuit boards known as <X>, <Y>, and <Z>. These boards have their own power supplies and provide emergency overspeed protection, flame detection, and the automatic synchronization signal. If two out of three boards "vote" for a trip, a shutdown is initiated by sending signals to the ETR's on the trip board. The automatic synchronization signal energizes an output relay on the trip board and, if two out of three TCEA boards agree, will close the generator's power circuit breaker. Each board has an 80196 microprocessor that runs a continuous loop program which is stored on firmware (EPROMs). The <P1> core is standard with firmware that does not change with each application and cannot be modified without changing EPROMs.

The <P1> core master protective functions (ETRs) will be covered in this section. Job specific master protective functions (PTR's) will be covered in the CSP and other turbine vendor documentation.

Figure 7-1 is a simplified block diagram of the protective functions provided by each board <X>, <Y>, and <Z> in the <P1> core.

The blocks used are representations of the firmware which can only be changed by replacing the EPROMs. The types of blocks used are as follows:

AND Logical AND function. All inputs must be "true" for the output to be "true".

COMPARE Compares two signals, with the output being defined by the text. For example, the software parameters are compared with the hardware jumpers. If they are not identical, a diagnostic alarm is generated. If the software and hardware are identical, the configuration information is sent on to the next block.

ISO Isolates and conditions signals from field devices to the levels used in the processors.

LATCH Latches the trip signal until reset manually.

LIMIT Limits the input to the range of the MAX and MIN values.

RANGE CHECK Limits the range of the output to within the limits defined by the MIN and MAX values. If the input is within range, the output equals the input. If the input is not within range, a diagnostic alarm will be generated.

A logic high or "1" from any trip signal will de-energize the ETR relays and cause the turbine to shut down. The status of the

<P1> core trip signals while in normal running condition is a logic low or "0".

I/0 CONFIGURATION

TO TRIP ANTICIPATOR CIRCUIT (SEE NEXT FIG.)

L12H_P

Figure 7-1. Simplified Block Diagram - TCEA Boards

The emergency overspeed trips that originate in the <P1> core are as follows:

1. High Pressure Shaft (HP) Overspeed Trip:

If the HP shaft scaled speed feedback exceeds the setpoint, an HP shaft overspeed trip will be initiated. This trip signal will be latched until a master reset command is given. For testing a different setpoint can be substituted for the design value.

2. High Pressure Shaft Over Deceleration Rate Trip:

If the HP shaft scaled speed feedback decreases faster than 100% per second, an HP shaft over-rate trip will be initiated. This fast rate of change usually indicates a defective speed sensor or wiring. This trip signal will be latched until a master reset command is given.

3. Low Pressure Shaft (LP) Overspeed Trip and LP Shaft Over Deceleration Rate Trip:

If enabled in a dual shaft system, these trips function in the same fashion as respective HP shaft trips.

4. Locked Rotor Trip:

Two additional protective functions are provided in the <X> and <Y> boards only (the boards are identical; jumpers are used to select the option). If the HP shaft speed is greater than 60% and the LP shaft speed is less than 1%, a trip will be initiated. Also, any time the HP shaft speed is less than 1% of rated speed a trip will be initiated.

5. Hardwired Trips:

Any pushbuttons or other hardwired trips initiated outside the Mark V LM control system will be connected to the PTBA terminal board in the <P1> core (see Appendix D, D-45). These hardwired trips will de-energize the 24 V dc supply from all the ETR and PTR relays. The <P1> core will also initiate a trip.

6. Cross Trip from <R>:

If the CSP in <R> initiates a trip to the PTR relays, a backup signal will be sent to the <P1> core to also trip the ETR relays.

7. LP Over Acceleration Trip:

If the LP shaft scaled speed feedback rate of change exceeds the setpoint, and the LP shaft speed exceeds the enable threshold, an LP overacceleration trip is initiated. This trip signal is latched until a master reset command is given.

This trip must be enabled in the I/O Configurator.

Each of these trip functions is derived independently by <X>, <Y>, and <Z>. In some LM applications, two speed signals are brought in to the <X> and <Y> boards only. The <Z> board is set with hardware jumpers to always initiate a trip for overspeed conditions. All of the hardware jumpers on the <X>, <Y>, and <Z> boards need to be set identical to each other. This creates a dual redundant system. The <X> and <Y> boards send their respective trip signals to their separate relays on the trip (TCTG) board. The two out of three voting takes place with the relay contacts. Throughout the documentation and drawings, the abbreviation "2/3" has been adopted to mean "two out of three”.

7-2.1. The Trip Board: TCTG

The trip board has four separate sets of three primary trip relays (PTR1, 2, 3 &4), and two separate sets of three emergency trip relays (ETR1 & 2). The PTRs are controlled from the TCQA board in the <R1> core, and the ETRs are controlled from the TCEA boards in <P1>. If two out of three PTRs or two out of three ETRs de-energize, the turbine will trip. The TCTG board also has three relays for synchronizing in addition to other auxiliary relays. Table 7-1 details which solenoid output will de-energize for a given relay output. The " √ " indicates this solenoid will de-de-energize if the relay is de-de-energized. See Appendix D for the signal flow diagrams.

Relays Solenoid 1 Solenoid 2 Solenoid 3 Solenoid 4

In document 2b - GEH-6353B MK 5 LM Panel Manual (Page 109-113)