Memory Consistency Property

A memory of a particular address is consistent if it holds the same value of at least one cache memory of the correspondent index. Otherwise, a memory is inconsistent. In the later case, a verdict of either true or false of a marker called dirty bit within cache memory architecture is switched accordingly. The dirty bit of the cache memory is true when cache memory and main memory of a correspondent address are inconsistent, otherwise, it is false. The correctness property of Memory Consistency can be formalised in Interval Temporal Logic (ITL) as follows:

` Memory[Addr] = Cache[X][Index] ∨ Cache[Y ][Index] ∨ Cache[Z][Index]

A memory of address Addr has to be equivalent with at least one of cache memory indexes, Index of processor X, Y or Z. If the above formula is met, then a memory is consistent.

Now I will show the outcomes of the execution of MATLAB scripts that have been run within AnaTempura. A shell script has been annotated within a Tempura program; this shell script “CheckProperty1.sh” is responsible for running the MATLAB and then executing MATLAB script “Property1.m”. The MATLAB script gathers and assigns the assertion data being created during the runtime of AnaTempura, and then plots these data in graphs for each state of the execution of the case study.

The number of states is 10, from state 0 until 9. Each single state is individually captured by this MATLAB script and representing data of every single state of the related rows and columns of the assertion data is in the text file as Figure6.10illustrates. For referencing the addresses of

main memory and the indexes of the cache memory, I use this format:

M emory[Addr] = Data Cache[P id][Index] = Data

Where,

Addr: indicates the requested address Pid: indicates the processor identification

Index: indicates the entry within the cache of Pid Value: indicates the data integer values

Noticed that, all the cache indexes is -8, while the main memory addresses data values is -16. Holding data -8 for the cache indexes means that cache indexes are empty and have no data yet. In contrast, a main memory holding data -16, means that the main memory is occupied and has data.

STATE0: By referring to Figures6.7&6.8, it can be found that the active processor is P id1

and always comes as the first graph of the plot, at top-left corner, while P id2, P id0are considered

idles. In this state, the P id1is the processor which requests to access address 14, Addr : 14. The

requested address fetches its data to the correspondent cache index of P id1 in case the access is

for reading RW = 0 (refer to Figure6.7).

When the access is for writing, RW = 1, then the processor writes directly to the correspon- dent cache index, Index[6], without updating the main memory. As the data of the main memory of the requested address is not updated yet and is different from the data of the correspondent cache index, the memory at state 0 is inconsistent. Once another processor requests the same ad- dress, this particular cache of P id1 fetches data 25 to that processor. When this particular cache

index of P id1 is replaced by another request, the old data gets copied into the correspondent

STATE 1: Processor P id1 writes to index 6 the data 0, Cache[1][6] = 0. The correspondent

address of this cache index, M emory[6], is inconsistent as it has the data -16. Interestingly, at the previous state the old data of Cache[1][6] was 25 and because it is replaced by a new data 0 in this state, the old data gets moved to its correspondent memory address M emory[14]. The main memory of address 6 M emory[6] is inconsistent. See Figure6.12.

STATE 2: Process P id2 requests to read address 2 and because address 2 is not available

in the cache index of all the three processors, the main memory fetches the data of address 2 to the requester processor. The main memory of address 2, M emory[2], and the cache index of processor P id2, index 2, Cache[2][2], have the same data, therefore, the main memory is

consistent. See Figure6.13.

STATE3: Processor P id2writes a new data 0 to index 0 which is the correspondent entry of

the requested address 0. The cache index of P id2 is index 0, Cache[2][0] = 0, while the main

memory of address 0 has different data M emory[0] = −16. Therefore, the main memory is inconsistent because it has not been updated yet. See Figure6.14.

STATE 4: Address 15 is requested to be read by processor P id0. Because the cache index

of the correspondent address is empty, the main memory of the requested address 15 fetches its data, M emory[15] = −16, to cache index 7 of P id0 as follows Cache[0][7] = −16. The main

memory of address 15 is consistent because it has at least one cache holding the same data. See Figure6.15.

STATE 5: Processor P id2 requests to read address 0 which is recently modified and written

to at state 3 by the same processor, P id2. The data written to this cache index 0 is 0, therefore,

cache index 0 of P id2 is Cache[2][0] = 0. The main memory of the requested address 0 is still

not updated M emory[0] = −16, therefore, the main memory is inconsistent. See Figure6.16.

STATE 6: The read request is initialised by processor P id1 to read address 4. As cache

index 4 is empty, the main memory fetches data -16 to this cache index. Cache index 4 of processor P id1is Cache[1][4] = −16, and the main memory of address 4 is M emory[4] = −16.

Consequently, the main memory is consistent. See Figure6.17.

STATE7: Processor P id2 requests to write to address 4 a new data 23. Index 4 of P id1 from

the previous state has got data -16 fetched by the main memory. At this state, index 4 writes new data by P id2. Now there are two different data Cache[1][4] = −16 and Cache[2][4] = 23.

Processor P id2 is the most updated, while P id1 is outdated at this state. Therefore, the main

memory of address 4 M emory[4] = −16, is outdated, and it is inconsistent. See Figure6.18.

STATE 8: Processor P id2 requests to read address 5. Because cache index 5 of processor 2

Cache[2][5] is empty, the main memory of address 5, M emory[5] = −16, fetches its data to the cache index, so it becomes Cache[2][5] = −16. As the cache memory of processor P id2 and the

main memory have the same data, the main memory is consistent. See Figure6.19.

STATE9: Processor P id1 requests to read address 9. Cache index 1, Cache[1][1], of this cor-

respondent address is empty, therefore, the main memory of address 9 fetches it data M emory[9] = −16 to this cache index, so it becomes Cache[1][1] = −16 which means that the main memory is consistent. See Figure6.20.