PCI Local Bus Interface 4
4.1 PCI Configuration
4.1.3 Message Signaled Interrupts 1
Message Signaled Interrupt (MSI) capability is optional for PCI 2.2 or 2.3, but required for PCI-X.
When Message Signaled Interrupts are enabled, instead of asserting an interrupt pin, the Ethernet controller generates an interrupt using a memory write command. The address and most of the data of the command are determined by the system and programmed in configuration registers. This permits the system to program a different message for each function so it can speed up interrupt delivery.
To enable Message Signaled Interrupts, the system software writes to the “MSI Enable” bit in the MSI “Message Control” register. When Message Signaled Interrupts are enabled, the Ethernet controller no longer asserts its INTA# pin to signal interrupts.
MSI systems allow a function to request up to 32 messages, but does not guarantee that all of them are allocated. The Ethernet controller supports only a single message. When Message Signaled Interrupts are enabled, the Ethernet controller generates a message when any of the unmasked bits in the Interrupt Cause Read register (ICR) are set to 1b. The Ethernet controller does not generate the message again until the ICR is read and a subsequent interrupt event occurs.
In conventional PCI mode, Message Signaled Interrupts can also be disabled in the EEPROM. If MSI is disabled, the Message Signaled Interrupt registers is not visible.
4.1.3.1 Message Signaled Interrupt Configuration Registers
Figure 4-3. Message Signaled Interrupt Configuration Registers 4.1.3.1.1 MSI Capability ID
Byte Offset Byte 3 Byte 2 Byte 1 Byte 0
F0h Message Control Next Capability MSI
Capability ID
F4h Message Address
F8h Message Upper Address
FCh Reserved Message Data
Bits Read/
Write
Initial
Value Description
Capability ID - Identifies the Message Signaled Interrupt register set in
4.1.3.1.3 Message Control
15 8 7 6 4 3 1 0
Reserved 64b Multiple
Enable
Multiple
Capable En
Bits Read/
Write
Initial
Value Description
0 R 0b
MSI Enable. If 1b, Message Signaled Interruptsa are enabled and the Ethernet controller generates Message Signaled Interrupts instead of asserting INTA#.
3:1 R 0b
Multiple Message Capable. Indicates the number of messages requested. The Ethernet controller only requests one message.
Register Number of messages
0 1
1 2 2 4 3 8 4 16 5 32
6 Reserved 7 Reserved
6:4 RW 0b
Multiple Message Enable. Written by the system to indicate the number of messages allocated. Since the Ethernet controller only supports one message, the system should never write a value other than 0b.
7 R 1b 64-bit capable. A value of 1b indicates that the Ethernet controller is capable of generating 64-bit message addresses.
15:8 R 0b Reserved. Reads as 0b.
a. Not applicable to the 82541xx or 82547GI/EI.
4.1.3.1.4 Message Address
4.1.3.1.5 Message Upper Address
4.1.3.1.6 Message Data
4.2 Commands
The Ethernet controller is capable of decoding and encoding commands for both PCI and PCI-X modes. The difference between PCI and PCI-X commands is noted in Table 4-5.
Bits Read/
Write
Initial
Value Description
31:0 RW 0b
Message Address – Written by the system to indicate the lower 32-bits of the address to use for the MSI memory write transaction. The lower two bits are always written as 0b.
Bits Read/
Write
Initial
Value Description
31:0 RW 0b
Message Upper Address – Written by the system to indicate the upper 32-bits of the address to use for the MSI memory write transaction.
Bits Read/
Write
Initial
Value Description
15:0 RW 0b
Message Data – Written by the system to indicate the lower 16 bits of the data written in the MSI memory write DWORD transaction. The upper 16 bits of the transaction are written as 0b.
Table 4-5. PCI and PCI-X Encoding Difference
C/BE
Encoding PCI Commands Abr. PCI-X Commands Abr.
0h Interrupt Acknowledge Interrupt Acknowledge
1h Special Cycle Special Cycle
2h I/O Read IOR I/O Read IOR
As a target, the Ethernet controller only accepts transactions that address its BARs or a configuration transaction in which its IDSEL input is asserted. In PCI-X mode, the Ethernet controller also accepts split completion for an outstanding memory read command that it has requested. The Ethernet controller does not respond to Interrupt Acknowledge or Special Cycle in either mode.
As a master, the Ethernet controller generates Read and Write commands for different causes as listed in Table 4-7. The addresses of these transactions are programmed either by system software or the software driver. The Ethernet controller always expects that they are claimed by one of the devices on the bus segment. The Ethernet controller never generates Interrupt Acknowledge, Special Cycle, I/O commands, or Configuration Commands.
Transaction burst length on PCI is determined by several factors, including the PCI latency timer expiration, the type of bus transfer (descriptor read/write or data read/write) made, the size of the data transfer (for data transfers), and whether the cycle is initiated by the receive or transmit logic.
Dh Dual Address Cycle DAC Dual Address Cycle DAC
Eh Memory Read Line MRL Memory Read Block MRB
Fh Memory Write & Invalidate MWI Memory Write Block MWB
Table 4-5. PCI and PCI-X Encoding Difference
C/BE
Encoding PCI Commands Abr. PCI-X Commands Abr.
Table 4-6. Accepted PCI/PCI-X Command as a Target
Transaction Target PCI Commands PCI-X Commands
Register or Flash Read MR,MRL,MRM,IOR MRD, MRB, AMR,IOR
Register or Flash Write MW, MWI,IOW MW, MWB, AMW,IOW
Configuration Read CFR CFR
Configuration Write CFW CFW
Memory Read Completion N/A SC
Table 4-7. Generated PCI/PCI-X as a Master
Transaction Cause PCI Commands PCI-X Commands
CMD RO
Tx Descriptor Read MR,MRL,MRM MRB 1
Tx Descriptor Write back MW,MWI MWB 0
Tx Data Read MR, MRL,MRM MRB 1
Rx Descriptor Read MR,MRL,MRM MRB 1
Rx Descriptor Write back MW,MWI MWB 0
Rx Data Write MW,MWI MWB 1
Message Signaled Interrupta MW MWB 0
Split Completion N/A SC N/A
a. Not applicable to the 82541xx or 82547GI/EI.
Following are a few specific rules:
•
For descriptor fetches, the burst length is always equal to the multiple of cache line sizes set by the transmit and receive descriptor fetch threshold fields. (See Section 3.2.4 and Section 3.4.1) For descriptor writes, the transfer size ranges from 8 bytes to N cache line's worth of data.Cache line sizes are: 16, 32, 64, and 128 bytes.