Harmonic Sources
3.7 Three-Phase Voltage-Source Conversion
3.7.1 Multi-Level VSC Configurations
Manufacturers are introducing high voltage drives rated above 200 kW using IGBT technology. However the switching transients caused by the higher voltages impose additional stresses on the motor windings. The multi-level solution has been developed to generate high voltage waveforms using relatively low voltage switching devices.
A multi-level voltage-source converter can switch its output between multiple volt-age levels within each cycle, thus creating a better voltvolt-age waveform for a particular switching frequency, when compared to a conventional two-level inverter. Theoret-ical phase output voltages for three- and five-level configurations are illustrated in Figure 3.53.
118 HARMONIC SOURCES
Figure 3.53 Phase output voltage waveforms for three- and five-level inverters. Source:
C. Newton, M. Sumner, ‘multi-level convertors: a real solution to medium/high-voltage drives?’, Power Engineering Journal, February 1998, pp. 21 – 26
1
0.8
0.6
0.4
0.2
0
Amplitude (normalised)
conventional two level five level
0 500 1000 1500 2000 2500
30 25 20 15 10 5
0 2 3 5 7
% THD
Number of levels
Figure 3.54 Comparison of phase voltage spectra and THD for multi-level inverters. Source:
C. Newton, M. Sumner, ‘multi-level convertors: a real solution to medium/high-voltage drives?’, Power Engineering Journal, February 1998, pp. 21 – 26
The reduced harmonic content achieved by the multi-level solution is further illus-trated in Figure 3.54, where the phase output voltage spectrum of a five-level inverter is compared with that of the standard two-level case. The figure also shows the voltage THD calculated for two-, three-, five- and seven-level output waveforms.
The following d.c.–a.c. multi-level configurations have been identified:
(1) Multiple bridge configuration, using transformer or inductor summing arrange-ments [22]. In this configuration the harmonic cancellation is achieved through the phase displacement of the voltage waveforms of phase-shifted transformer secondary windings.
(2) Multiple bridge using direct series connection [23]. This is a variation of the previous case, its main difference being the elimination of the phase-shifting transformers, i.e. it is directly connected to the a.c. side. Each phase consists of series connected single-phase full bridges, each bridge requiring an isolated d.c. bus.
(3) The level diode clamped converter [24]. This alternative achieves the multi-level waveforms by the series or parallel connection of switches within the converter bridge itself.
(4) The multi-level flying capacitor converter [25]. In previous configurations each phase leg consisted of a switch pair in parallel with a bus capacitor, and must be always connected to either the positive or negative node of the capacitor. In this alternative the switch pair/capacitor cell is isolated and inserted within a similar cell. Thus this inner pair of switches/capacitors now ‘fly’ as the outer pair of devices switch.
(5) The chain circuit converter [26]. This configuration consists of individually con-trolled units, which can then be assembled to form the three-phase converter. It provides modularity and ease of expansion.
(6) A d.c. voltage reinjection scheme [27]. Unlike the previous multi-level configura-tions, where all the switches form part of the main conversion process, the pulse increase is now achieved by separate switching circuitry at reduced current levels.
3.8 Inverter-Fed A.C. Drives
Although the thyristor-controlled d.c. drive still holds a large share of the market in the large power rating group, the emphasis has shifted towards the use of inverters and induction motors. This trend has been helped by substantial increases in the ratings of the more controllable GTO thyristors and IGBT switching devices.
The basic three-phase inverter bridge commonly used for a.c. motor control is made up of six controlled semiconductors, each having a feedback diode connected in inverse parallel, as shown in Figure 3.55. The inverter can be of the voltage source (VSI) or current source (CSI) types. The VSI requires a constant d.c. voltage input, which is normally achieved with a large capacitor or LC filter, whereas the CSI needs a constant current input, obtained by means of a series inductor in the d.c. link. CSI drives have better speed characteristics but require a motor with leading power factor (either synchronous or induction-type with capacitors); however, the use of turn-off switching devices removes this restriction.
+
− d.c. bus input
1 3 5
2 6
4
A B
I II III IV V VI 1 2 3 4 5 6 2 3 4 5 6 1 3 4 5 6 1 2
N
C
Figure 3.55 Basic three-phase inverter and balanced motor load showing an elementary switch-closing sequence
120 HARMONIC SOURCES
The inverter bridge is normally supplied from a line-commutated controlled converter and thus, the harmonic content injected into the a.c. power system is as described in Section 3.6 (for the CSI drive) or Section 3.7 (for the VSI drive).
Motor Phase Voltage In the circuit of Figure 3.55 the inverter phase output voltage is always at one of two distinct voltage levels. The floating neutral voltage with respect to ground, expressed in terms of the inverter phase output voltage waveforms vA, vB, vC is
vN = 1
3(vA+ vB+ vC) (3.82)
so that a typical motor phase voltage is vAN = vA− vN = 1
3(2vA− vB− vC) (3.83) For a balanced linear, bilateral motor load impedance, the motor phase voltage of a harmonic of order n can be expressed as
vAN (n) = 1
3[2vA(n)− vB(n)− vC(n)]
= 1
3[2vmnsin(nω1t)− vmnsin(n(ω1t+ 2π/3)) − vmnsin(n(ω1t− 2π/3))]
= 2
3vmnsin(nω1t)[1− cos(2nπ/3)]
= 2
3vA(n)[1− cos(2nπ/3)] (3.84)
and similarly for phases B and C:
vBN (n)= 2
3vB(n)[1− cos(2nπ/3)] (3.85) vCN (n)= 2
3vC(n)[1− cos(2nπ/3)] (3.86) Moreover, for all the positive and negative sequence harmonics
cos(2nπ /3)= −1 2 so that
vAN (n)= vA(n), vBN (n)= vB(n), vCN (n)= vC(n) (3.87) and in the balanced three-phase system, for the zero sequence harmonics,
cos(2nπ /3)= 1
Switch V sequence
1
0 vA/vBUS
1
0 vB/vBUS
1
0 vC/vBUS
2/3 1/3
−1/3
−2/3 0 vAN/vBUS
VI I II III IV V VI I II III IV
2/3 1/3
−1/3
−2/3 0 vBN/vBUS
2/3 1/3
−1/3
−1/3 0 vCN/vBUS
Figure 3.56 Basic six-step waveforms
so that
vAN (n)= vBN (n)= vCN (n)= 0 (3.88)
Thus, for the basic six-pulse voltage sourced inverter, the motor phase input voltage is identical to that of the corresponding inverter phase output voltage, with the exception that all inverter phase triplen harmonics have been eliminated. The effect of triplen harmonic elimination is shown in Figure 3.56 for the inverter output voltage waveforms resulting from the basic switch-closing sequence indicated in Figure 3.55. Since each motor phase input waveform results from square inverter phase voltage waveforms, the motor phase voltage in the frequency domain is
vp= 2 πvBUS
∞ k=0
1
(6k+ 1)sin((6k+ 1)ω1t)+ 1
(6k+ 5)sin((6k+ 5)ω1t)
(3.89)
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Magnetising Current and Flux The motor phase magnetising inductance, Lm, acts as an integrating filter for the input voltage waveform, i.e.
ip= 1 Lm
t t0
vpdt (3.90)
Therefore for the nth harmonic phase voltage vp(n)= 2
and the magnetising current resulting from equation (3.89) is
ip= 2vBUS For a motor phase magnetising inductance of an equivalent N turns, the resultant motor phase air gap flux phasor is
φp= 2vBUS The relative amplitudes of these motor phase harmonic quantities are summarised in Table 3.8.
Voltage Control and its Effect on Harmonics The peak amplitude of the funda-mental frequency voltage in equation (3.89) is
vp(1)= (2vBUS)/π
and from equation (3.94) the peak amplitude of the fundamental air gap flux phasor is φp(1) = 1
ω1N 2vBUS
π = vp(1)
ω1N (3.95)
Table 3.8 Relative amplitudes of motor phase harmonics
Quantity Harmonic number, n
1 5 7 11 13 17 19 23 25
vp 1.000 0.200 0.143 0.091 0.077 0.059 0.053 0.043 0.040
ip 1.000 0.040 0.020 0.008 0.006 0.004 0.003 0.002 0.002
φp 1.000 0.040 0.020 0.008 0.006 0.003 0.003 0.002 0.002
To maintain φp(1) constant when the fundamental frequency ω1 varies, it is evident from equation (3.95) that vp(1) must be made a linear function of ω1.
Some high-power inverter-fed a.c. motor speed controllers employ a separate d.c.
chopper power supply in the d.c. bus to vary the voltage linearly with frequency. In this case the inverter output voltage waveforms are always square waves, as shown in Figure 3.56, and the air gap harmonic flux vectors have the relative amplitudes indicated in Table 3.8.
An alternative to independent d.c. voltage control is the use of pulse width modula-tion, discussed in the next section.
Pulse Width Modulation A popular drive configuration consists of a VSI operating on the PWM concept in order to economise on power semiconductor switching stages.
The operating principle consists of chopping the basic inverter square wave output voltage of Figure 3.56 in order to control the fundamental frequency voltages.
In its simplest form a saw-tooth wave [28] is used to modulate the chops, as shown in Figure 3.57. The saw-tooth has a frequency which is a multiple of three times the sine wave frequency, allowing symmetrical three-phase voltages to be generated from a three-phase sine wave set and one saw-tooth waveform. This method controls line-to-line voltage from zero to full voltage by increasing the magnitude of the saw-tooth or a sine-wave signal, with little regard to the harmonics generated.
The most significant areas of voltage in the spectrum, apart from the fundamental, occur at the carrier frequency (saw-tooth frequency) and its two sidebands, and to a significant extent at each multiple of these frequencies in the spectrum. When the carrier frequency is six times the fundamental, the triplen harmonics cancel in the system;
however, the phase waveforms of Figure 3.57 do not have half-wave symmetry, hence even harmonics are present.
If the carrier frequency is a large multiple of the fundamental, the first large har-monics encountered are high in the harmonic spectrum.
Single-phase bridge inverters can use either bipolar or unipolar PWM switching schemes. With bipolar switching two legs of the bridge are synchronised so that either +Vd or −Vd appears across the load. The harmonics in the inverter output voltage
0
0 +vd
−vd
Carrier wave Sine wave signal
Upper thyristor on
Lower thyristor on Per phase output
voltage (with respect to d.c. centre tap)
p
Figure 3.57 Principle of PWM
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1.2
1 mf
(mf + 2) (2mf + 1) mα = 0.8, mf = 15
(3mf + 2)
2mf 3mf
1.0 0.8 0.6 0.4 0.2 0.0
Harmonics h of f1 (VA0)h
Vd/2
^
Figure 3.58 Harmonic spectrum with bipolar switching
are sidebands centred around the switching frequency and its multiples, as shown in Figure 3.58, the harmonic orders being given by:
• h = kmf ± n
where mf is the frequency modulation ratio, and k and n are integers.
For odd values of k, harmonics only exist for even values of n and vice versa.
With unipolar switching, each leg of the inverter is controlled independently so that there are periods when both sides of the load are connected to the same d.c. rail, resulting in zero output voltage. This has the effect of doubling the switching frequency as now the harmonics present are given by:
• h = k2mf± n.
The spectrum for the unipolar switching scheme is shown in Figure 3.59.
PWM with Selected Harmonic Elimination More efficient PWM techniques have been developed to control the fundamental and harmonic voltages simultaneously [29–32]. For this purpose the chops can be created at predetermined angles of the
1 mf
h (2mf + 1)
(2mf − 1)2mf 3mf 4mf 1.0
0.8 0.6 0.4 0.2 0
(Harmonics of f1) (V0)h
Vd
^
Figure 3.59 Harmonic spectrum with unipolar switching
0° 180°
180° − a3180° − a2
180° − a1
a1 a2 a3
Figure 3.60 PWM wave on the basis of selected harmonic elimination by a look-up table
60
00 20 40 60 80 100
10
Notch angles (degrees) 20 Harmonic magnitude (percentage of fundamental)
Fundamental voltage (percentage of maximum fundamental) 30
40
a3
a2
a1 50
40 80 11th harmonic 120
13th harmonic
160 200
Figure 3.61 Notch angle curves with voltage control and selected elimination (for 5th and 7th harmonics)
square wave as shown in Figure 3.60. By way of example, Figure 3.61 illustrates the case where the fifth and seventh harmonics are eliminated with the help of a look-up table storing the angles required.
In the method of reference [32] the period is divided into six regions. If the second and fifth regions of each phase waveform are filled with a train of pulses, or chops, only these pulses appear in the line-to-line voltage.
Harmonic voltages occur at multiples of the carrier frequency (i.e. the chop number per half-wave of the phase voltage (m) times six) with sidebands, given by L(6m± 1), where L= 1, 3, 5, 7.
Here also the carrier is a triplen harmonic and is cancelled out in a three-phase system. Moreover, the phase waveforms have such symmetry that there are no even harmonics. The higher m is, the higher up the spectrum the harmonic voltages occur.
The number of inverter switchings per second, F (2m+ 1), limits the number of chops allowable as fundamental frequency increases, e.g. for eight chops there are 17 on/off switchings per period.
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In order to keep harmonic orders high in the spectrum, the number of chops is changed as fundamental frequency increases.
Further reduction of lower-order harmonics can be achieved by the use of complex PWM control waveform strategies, at the cost of increasing the inverter switching rate.
For a given maximum inverter phase switching rate, the problem is to choose that PWM control strategy which will achieve the desired linear variation of fundamental voltage amplitude with frequency and reduce the effect of harmonic torques, or minimise the harmonic power losses within the motor.
Generally, at any fundamental switching frequency, each chop per half cycle of the inverter phase voltage waveform can eliminate one harmonic of the waveform or reduce a group of harmonic amplitudes [29]. Thus for m chops per half cycle one chop must be utilised to control the fundamental harmonic amplitude, so m− 1 degrees of freedom remain. The m− 1 degrees of freedom may be utilised to eliminate completely m− 1 specified low-order harmonics or to minimise motor power losses caused by a specified range of harmonics within the motor.
At any fundamental frequency, elimination of the lower-order harmonics from the phase waveforms will cause the portion of the r.m.s. which was provided by the elim-inated harmonics to be spread over the remaining harmonic magnitudes. This occurs because the total harmonic r.m.s. voltage cannot change. The effect of this shifting motor performance needs to be determined, but the integrating filter characteristic of the motor should be more effective in reducing the current harmonics at higher orders.
Multi-Stepped Converters Rather than increasing the frequency of the PWM pattern to reduce the harmonic content of the output voltage, a multi-bridge configuration with parallel connected units can be subjected to a phase-shifted carrier, as shown in Figure 3.62. Considering n units, each carrier is shifted by T /n, where T is the period of the fundamental reference wave. Thus the voltage harmonic components of the individual units are shifted with respect to each other and can be designed to be cancelled when the outputs of the various bridges are added. In the case illustrated in Figure 3.62(b) the carrier to fundamental frequency ratio is 9 and thus the individual bridges have harmonic orders around the 9th and multiples of it. However, the use of four units produces the spectrum shown in Figure 3.62(e), where the lowest dominant harmonic orders are in the region of the 36th.