Operation

In document A Mössbauer study of spin relaxation of ⁵⁷Fe ions (Page 168-171)

Mössbauer spectrometer

3 Operation

3.1 Basic principles

Mössbauer spectra are usually accumulated in a multiscalar mode of operation, where each channel of the spectrum is opened for the same length of time during a linear velocity sweep. Because of possible jitter in the computer processor and the varying length of instructions, the computer program and the interface were controlled by a crystal clock in the interface (figure 3). In this way, the intervals for which the counters were open could be made exactly constant, ensuring a flat baseline, and the analog velocity sweep could be made as smooth as possible.

Figure 1 shows the basic synchronizing loop programmed within the computer. The clock sets a flag w ithin the interface, and the state of this flag is tested by the computer. If set, the computer proceeds to the next instruction, which is to output the X digital signal (the velocity sweep), resetting the flag. Time is then available before the next clock pulse to perform

Time 0 ps 50 ps Test flag Output X Reset flag Input counts Output Y Test flag Other computations etc

re 1 TThe basic instruction loop used to synchronize :omputeer operations with the interface

r essenntial tasks, such as reading out the display and ng in t the counts. After finishing the computation, the puter wvails until the flag is once again set by the interface, ing o f lithe computer program to ensure that the computa- can hoc performed in the time available is necessary. :tuse o f ' the timing requirements, it was advantageous in e placets to group these loops in pairs, leaving out the ng o f thhe flag for the second time to increase the available putatioon time. The interface Hag was still set by the clock

reset byy the output o f the X digital signal,

was ddccided to use a velocity reference signal similar hat propposed by Cranshaw (1964), that is, a linear ramp ng the data accumulation period followed by a flyback od, conmmonly half the ramp period. The computer is »rammeed around this basic cycle, and the flow diagram is n in lipgure 2. After the initiali/m g steps, the program red thee main loop, composed of a linear velocity sweep od, andd a flyback period. During the sweep period, the nts weree read in and a selected subgroup displayed. During flybackk period, grouping information was read in and, n requiiired, clearing or printing out o f groups were carried It wass considered desirable to maintain the frequency of sweep aas high as possible (but less than 20 I I / ) to minimize curvatilure o f the spectra baseline due to the varying tion o f f the source during the velocity sweep. It was found iiblc, uusing careful programming, to achieve a sweep uency c o f 13 Hz.

Hiring t the time o f the linear sweep the incoming counts iceumuulalcd in eight counters of six bit accuracy (figure 4). se counntcrs are accessed in sequence by the interface, and • contecnts placed in a buffer connected to the computer it. Afteer each counter has been accessed, it is cleared and

Figure 2 The program flow diagram

counting resumed. The computer then adds the contents of the buffer into the current memory location, and advances to the next location. In this way the eight M össbauer spectra arc interleaved within the computer memory. Each counter is open for 198 ps (with 2 ps dead time) and this, combined with the number o f bits in the counters limits the maximum usable count rate to about 200 k per second per block of 256 channels.

In our interface, because o f the availability of two DR11C inputs, the subgroups are treated in pairs, and four lots o f two are moved cyclically into the input buffers, and hence into the computer. This also leads to a saving of computer time.

Grouping into blocks o f more than 256 channels is done in the interface by addressing the counters out o f sequence. Tor example, if the counter sequence for 8 x 256 is A l l C D E F G H etc., then for 2 x 1024 it would be A l l A l l A l l A B etc. Possible combinations are shown in table I.

Table 1

Grouping Butler sequence

8 x 256 2x512, 4x256 4x512 2 x 1024 A l l C D E T C H etc. A B ( I) A l l 67/ etc. A l l C D A l l C D etc. A l l A l l A l l A B etc.

A sw itch on the interface allows the selection of one of these four possible groupings (figure 3).

B W indiou, B L Hickson. P R outdiffe and K K P Srivastava 10 gs 0 5 ms

. ui y

I 0 5 us I *is

1 y u

I- --- 1 0 5 /js| r

ü , y ! y y

2 ms 0 5 ms \ 7

Y

r New d'ita i ready J ? DRIIC«2 { ! M l' Req B OR 0 0 2 L«J° 1 > OP BIT IS , OR 1102 Ground IP BIT M3 DR H O I ® ~ « $ ;m r TP BIT 04

X-\

Sub<3roupin^ o ; , ® - « 1 b 4 control OR I IC** I OP BI T 115®— * -* L--- Ground DR IIC #2 2 A

!d

®

v j

|

A

i ! Blocking To data registers and multiplexors 4 3 2 I 1 1 I I Clear Transfer

Figure 3 The clock and sequencer circuits which control the cormputer and interface operations

3.2 Tinning details

The I OK) kHz crystal clock delivers 0 5 /ts pulses separated by 50 /<s ((figure 3), and these pulses operate the scale of four scquentcer circuit. This circuit activates one o f the four outpufis according to the grouping selector, selecting a pair

o f buffer counters to be accessed. This output combines with pulses derived from the clock (after a small delay to account for propagation time) to block the incoming counts to this counter, place the contents on the input to the bufTer registers, transfer these contents, and clear the counters (figures 3 and

Blocking Transfer Blocking Counters r , Print " A Groujnd J Request B ^ DR HC« I Zero 1 Input 3 DR MC**2 Blocking 1234 ibisi IP BIT I DR IlCtttl I '—Ground', Pulse inputs i p b i t i2o y g DR I IC**»I £ OP B1IT l5o—— DR Il(C*»2

Figure? 4 Details of the buffer registers and multiplexors which allow up to eight simultaneous data channels

^ scries »if positive edge triggered monoslahles arc used to Juce delayed pulses for performing these circuit functions. :r a delay of 10 /<s the clock also sets the flag being tested he computer (figure 3). The first instruction after the test itisfied. the output of the X digital signal, resets the flag, g the 'New data ready' signal o f DR 11C #2. The computer l reads in the counts from the two input buffers, and brms other tasks. The next clock pulse gates the X digital ja I in the output register o f DR I K ' #2 into the 12 bit er connected to the digital ts> analog converter (figure 5). i the interval from 10 /<s to 50 ps with respect to the clock computer must input the counts and output the X and Y

BITS

In document A Mössbauer study of spin relaxation of ⁵⁷Fe ions (Page 168-171)