Operation modes

The CPU can be placed into the following operation modes: stop, wait, background and security.

10.4.1 Stop mode

Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 V6 can be configured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU from stop mode.

When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bit has been set by a serial command through the background interface (or because the MCU was reset into active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this case, if a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode.

10.4.2 Wait mode

The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally.

If a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in wait mode.

While in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status

commands are available while in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the CPU is in either stop or wait mode. The BACKGROUND command can be used to wake the CPU from wait mode and enter active background mode.

10.4.3 Background mode

Background instruction (BGND) is not used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode waiting for serial background commands. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.

Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program.

The active background mode functions are managed through the background debug controller (BDC) in the HCS08 V6 core. The BDC provides the means for analyzing MCU operation during software development. Active background mode is entered in any of the following ways:

• When the BKGD/MS pin is low at the time the MCU exits reset.

• When a BACKGROUND command is received through the BKGD pin.

Operation modes

• When a BGND instruction is executed.

• When encountering a BDC breakpoint.

Background commands are of two types:

• Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include:

• Memory access commands

• Memory-access-with-status commands

• BDC register access commands

• The BACKGROUND command

• Active background commands, which can be executed only while the MCU is in active background mode. Active background commands include commands to:

• Read or write CPU registers

• Trace one user program instruction at a time

• Leave active background mode to return to the user's application program (GO) The active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time.

The active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed.

10.4.4 Security mode

Usually HCS08 V6 MCUs are implemented with a secure operating mode. When in secure mode, external access to internal memory is restricted, so that only instructions fetched from secure memory can access secure memory.

The method by which the MCU is put into secure mode is not defined by the HCS08 V6 Core. The core receives an external input signal that, when asserted, informs to the core that the MCU is in secure mode.

While in secure mode, the core controls the following set of conditions:

1. The RAM, flash, and EEPROM arrays are considered secure memory. All registers in Direct Page or High Page are considered non-secure memory.

2. Read data is tagged as either secure or non-secure during a program read, depending on whether the read is from secure or non-secure memory.

3. A data read of secure memory returns a value of $00 when the current instruction is tagged as non-secure or the access is a BDC access.

4. A data write to secure memory is blocked and data at the target address does not change state when the current instruction is tagged as non-secure or the access is through BDC.

5. A data write to secure memory is never blocked during the stacking cycles of interrupt service routines.

6. Data accesses to either secure or non-secure memory are allowed when the current instruction is tagged as secure.

7. BDC accesses to non-secure memory are allowed.

When the device is in the secure mode, secure memory is treated the same as non-secure memory, and all accesses are allowed.

Table 10-2 details the security conditions for allowing or disabling a read access.

Table 10-2. Security conditions for read access

Inputs conditions Read control

Security enabled

Ram, flash or EEPROM

access

Program or

vector read Current CPU instruction

from secure memory Current access

is via BDC Read access allowed

0 x x x x 1

1 0 x x x 1

1 1 1 x x 1

1 1 0 1 0 1

1 1 0 1 1 0

1 1 0 0 0 0

1 1 0 0 1 0

Operation modes