Power Management 6
6.3 D3 cold support
6.3.3 PCI Power Management Registers
Power Management registers are part of the capabilities linked list pointed to by the Capabilities Pointer (Cap_Ptr) in the PCI configuration space. Refer to Section 4.1.
All fields are reset by LAN_PWR_GOOD. All of the fields except PME_En and PME_Status are reset by the deassertion (rising edge) of RST#. If AUX_POWER = 0b, the PME_En and
PME_Status fields also reset by the deassertion (rising edge) of RST#.
The following table lists the organization of the PCI Power Management Register Block:
The following sections describe the register definitions, whether they are required or optional for compliance, and how they are implemented in the Ethernet controller. Complete details can be found in the PCI Power Management Interface specification.
Note: The offset indicated is the byte-offset from the position indicated by Cap_Ptr in the Configuration Space Header.
6.3.3.1 Capability ID
1 Byte Offset = 0 (RO)
6.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO)
Byte Offset Byte 3 Byte 2 Byte 1 Byte 0
DCh Power Management Capabilities
(PMC) Next Item Ptr Capability ID
E0h Data
PMCSR_BSE Bridge Support
Extensions
Power Management Control / Status Register (PMCSR)
Bits Default R/W Description
07:00 01h Read
Only
ID – The Ethernet controller returns a value of 01h for this field, indicating the linked list item as being the PCI Power Management Registers.
Bits Default R/W Description
6.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO)
Bits Default R/W Description
15:11 See text Read Only
PME_Support – This 5-bit field indicates the power states in which the function may assert PME#a. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state.
bit (11) (XXXX1)b – PME# can be asserted from D0 bit (12) (XXX1X)b – PME# can be asserted from D1 bit (13) (XX1XX)b – PME# can be asserted from D2 bit (14) (X1XXX)b – PME# can be asserted from D3hot bit (15) (1XXXX)b – PME# can be asserted from D3cold
If Power Management is not disabled in the EEPROM, the Ethernet controller supports PME# generation from D0 and D3hot states. If Power Management is not disabled and AUX_POWER = 1b, the Ethernet controller also supports the D3cold state.
Condition Value
00000b Power Management disabled in EEPROM
AUX_POWER = 01001b Power Management enabled, AUX_POWER = 11001b Power Management enabled,
a. Not applicable to the 82541ER.
10 0b Read
Only
D2_Support - If this bit is set to 1b, supports the D2 Power Management State.
The Ethernet controller returns a value of 0b for this bit indicating that it does not support D2 and cannot handle the PCI clock stopping in PCI 66 MHz mode (or PCI-Xb mode) without RST# being asserted.
b. Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.
09 0b Read
Only
D1_Support - If this bit is set to 1b, supports the D1 Power Management State. The Ethernet controller returns a value of 0b for this bit indicating that it does not support D1.
08:06 000b Read
Only
AUX Current – Specifies the auxiliary power current required for PME#
generation from D3cold if the Data Register is not implemented.
05 1b Read
Only
DSI – The Device Specific Initialization bit indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. The Ethernet controller returns a value of 1b for this bit indicating that it’s device driver must be executed following transition to the D0 uninitialized state.
PME_Clock - When this bit is a 1b it indicates that the function relies on the presence of the PCI clock for PME# operation. The controller loads this bit from the EEPROM. Otherwise, it returns a 0b.
02:00 010b Read
Only
Version - A value of 010b indicates that this function complies with the Revision 1.1 of the PCI Power Management Interface Specification.
6.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)
Bits Default R/W Description
15 0b (see
description)
Read/
Write 1b to clear
PME_Status – This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. The Ethernet controller returns a value of 1b for this bit if a Wakeup condition has been detected.
Writing a 1b clears this bit and deasserts PME#a.
If the AUX_POWER input is 1b, the PME_Status field is only reset by LAN_PWR_GOOD. If AUX_POWER is 0b, PME_Status is also reset on the deassertion (rising edge) of RST#.
14:13
Data_Scale - This 2- bit read-only field indicates the scaling factor to be used when interpreting the value of the Data register. This field outputs 01b (to indicate units of 0.1 watt) when Manageability is enabled in the EEPROM and the Data_Select field is set to 0, 3, 4, or 7, and 00b otherwise.
12:09 0000b Read/
Write
Data_Select - This 4-bit field is used to select which data is to be reported through the Data register and Data_Scale field. These bits are only writable when Power Management is enabled via EEPROM.
08 0b on Power-On reset
Read/
Write
PME_En – If Power Management is not disabled in the EEPROM, writing a 1b to this register enables Wakeup and causes the Ethernet controller to assert PME# when it receives a Wakeup event enabled in the Wakeup Filter Control Register (WUFC).
Note: This bit cannot be set for the 82541ER.
If Power Management is disabled in the EEPROM, writing a 1b to this bit has no affect, and does not set the bit to 1b.
If the AUX_POWER input is 1b, the PME_En field is only reset by LAN_PWR_GOOD. If AUX_POWER is 0b, it is also reset on the deassertion (rising edge) of RST#.
Note: If APM Wakeup is enabled, the PME# pin can be asserted even if PME_En is 0b. See Section 6.4.1 for details.
07:02 000000b Read
Only Reserved - The Ethernet controller returns a value of 000000b for this field.
01:00 00b Read/
PowerState - This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is as follows:
00b - D0
01b - D1 (ignored if written with this value) 10b - D2 (ignored if written with this value)
6.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO)
This register indicates support for PCI bridge specific functions. Note that these functions are not implemented in the Ethernet controller and the values are set to 00h.
6.3.3.6 Data Register 1 Byte Offset = 7 (RO)
This register is used to report power consumption and heat dissipation. Its value and meaning is determined by the value programmed in the Data_Select field of the Power Management Control/
Status Register (PMCSR).
The units are defined by the Data_Scale field of the Power Management Control/Status Register.
If power management is disabled in the EEPROM, then the data register always reads 0b.
Bits Default R/W Description
07:00
00h (loaded from EEPROM)
Read Only
Data returned.
See the following explanation.
Data Select Meaning
0 D0 Power Consumed
1 D1 Power Consumed
2 D2 Power Consumed
3 D3 Power Consumed
4 D0 Power Dissipated
5 D1 Power Dissipated
6 D2 Power Dissipated
7 D3 Power Dissipated
8 Common power consumption of multi-function devices
9-15 Reserved
Data Select Meaning
0 Unknown (used for unsupported states)
1 0.1 Watts (used by Ethernet controller for supported states)
2 0.01 Watts
3 0.001 Watts
If power management is not disabled and when the Data_Select field is programmed to 0 or 4, the Ethernet controller sets the Data Register to the D0 Power value in the EEPROM. When the Data_Select field is programmed to 3 or 7, the Ethernet controller sets the Data Register to the D3 Power value in the EEPROM. Otherwise it returns 0b.
6.4 Wakeup
The Ethernet controller supports two types of wakeup mechanisms:
•
Advanced Power Management (APM) Wakeup•
ACPI Power Management WakeupNote: The 82541ER contains power management logic, but is not spec-compliant, because it does not assert PME# for Magic Packets, Network Wakeup Packets, or link change status.
The ACPI Power Management Wakeup uses the PME# pin to wake up the system. The Advanced Power Management Wakeup uses the PME# pin.