ADC Power Consumption Discussion

A key metric in an ADC is the energy required per conversion. This is particularly important in this application, where the sampling rate is less important. We present here a discussion of power consumption and energy per conversion, as it pertains to the proposed ADC architecture.

Ignoring leakage currents, there is no static power consumption by the digital counter. Consequently, the energy consumed by the counter per conversion is fixed, and independent of the sampling time (but data-dependent, with higher counts consuming more energy due to the number of switched transistors). While less obvious, a similar result can be obtained for the Schmitt-trigger oscillator. The average current through the current-starved inverter leg of the oscillator is:

hIinvi = Cosc

∆VSchmitt

Tosc/2

= 2Cosc∆VSchmittfosc= Ictrl, (7.5)

7.2 Control

The average current drawn by the oscillator is then:

Iavg = Ibias−network + hIinvi + ISW,Schmitt= 3Ictrl+ ISW,Schmitt, (7.6)

where Ibias−network is the power consumed by the bias network of Figure 7.6 (2Ictrl), and

ISW,Schmittis the dynamic current consumed at each switching interval in the Schmitt trigger

itself. If we (for now) assume that ISW,Schmitt is negligible (compared to the dynamic and

static currents from the other components of Figure 7.6), Eq. 7.6 can be used to express the approximate average power consumption of the ADC as:

Padc= 3VDDIctrl. (7.7)

The energy per conversion required from the oscillator is simply the average power drawn times the sampling time:

Econv= 3VDDIctrlTsample (7.8)

Econv= 3VDD2Cosc∆VSchmittfoscTsample = 6VDDCosc∆VSchmittKF, (7.9)

where KF is the final value of the digital counter (equal to foscTsample) after the sampling is

complete. We see that the energy per conversion of the oscillator is data-dependent, but it is not dependent on the sampling time. We should also point out that to minimize the energy required per conversion, it is desirable to keep Cosc and ∆VSchmitt as small as possible.

Reducing either of these two values too much, however, increases the noise of the oscillator. Making ∆VSchmitttoo small makes the transition times of the Schmitt trigger susceptible to

small variations in transistor threshold values and increases the coupling between voltage noise on the capacitor and jitter in the frequency output. A small change (noise) in voltage can then have a large impact on the frequency output. Similarly, making the capacitor Cosc

too small increases the kT

C noise at the input of the Schmitt trigger.

Integrated Distributed MPPT in 0.35µm CMOS

mation that ISW,Schmitt is negligible is no longer valid. For ultra low-power designs, low

power Schmitt trigger circuits [50,51] must be investigated, or other more suitable oscillator circuit employed.

The voltage to current converter does in fact consume static power during a conversion, so the energy per conversion will depend on the sampling time2_{. The power consumed by}

the translinear voltage to current converter of Figure 7.4 is given by

P = 6VDDIbias. (7.10)

The factor of 6 in this equation comes from the six branches that carry the bias current in Figure 7.4. This factor can be reduced by appropriately scaling the bias network transistors to carry only fractions of the required bias current for the translinear circuit, but the mini- mum value of the coefficient must be larger than 3 (for the two legs of the translinear circuit block, as well as the output current mirror, all of which must carry the full Imathrmbias). In

this work, all transistor were scaled to carry the same bias current. To reduce the power of the voltage-to-current converter, it is desirable to reduce Ibias. The energy required per

conversion is given by

Econv= 6VDDIbiasTsample =

6VDDIbiasK

fosc

= 6VDDIbiasK (Vhigh− Vlow)KviKif

. (7.11)

Therefore, to minimize the energy per conversion in the voltage-to-current converter, we want to make the parameter Kvi as large as possible, and Ibias as small as possible. Kvi

can be made large by using a small value of R in the translinear amplifier. However, since we are limited by the fact that Ibias/2 must be larger than i, we can not increase Kvi

arbitrarily, without also increasing Ibias/2. Thus, the best we can do is to try make i a

large fraction of Ibias. However, as discussed earlier, as i becomes a larger fraction of Ibias,

the linearity of the voltage to current converter deteriorates, which may decrease ADC 2

For the analysis considered here, we assume that the ADC can be turned off (power gated) when a conversion is not taking place. For simplicity, such mechanisms were not implemented in the experimental prototype, but it can be done by the addition of just a few transistors.

7.2 Control

Duty cycle

S

R

PWM OUT

f

digital counter

Digital_Comparator

count

Figure 7.10: High-level schematic drawing of counter-based digital pulse-width modulator imple- mentation.

overall performance. In a given design, there is thus a certain i to Ibias ratio that gives

the best power efficiency to linearity trade-off. As the voltage-to-current converter stage is scaled with this ratio constant, the energy per conversion is yet again constant. This is because as the absolute values of Ibias and i are increased, the sampling time Tsample can

be correspondingly reduced, leading to a constant energy per conversion.

We thus note that for a given design where the power/linearity trade-off has been made, the energy required per conversion for this ADC architecture is constant. However, at very low power levels the power losses that have been ignored in this analysis (e.g. counter leakage currents, Schmitt-trigger dynamic and static power consumption) will become large enough such that their contributions must be taken into account.