Process Optimization - Development of inversion-mode and junctionless Indium-Gallium-Arsenide M

The process optimization is performed using the Lagrange criterion, which is based on the cal- culation of the Hessian determinant H of ˆY [4]:

H = ∂2_Yˆ ∂X2 1 ∂2_Yˆ ∂X1∂X2 ∂2_Yˆ ∂X2∂X1 ∂2_Yˆ ∂X22 = ∂ 2_Y_ˆ ∂X₁2 ! ∂2Yˆ ∂X₂2 ! − ∂ 2_Y_ˆ ∂X2∂X1 ! ∂2Yˆ ∂X1∂X2 ! (A.10) The following four possible situations enable to determine the nature of the critical point of the response function:

• H > 0 and ∂2Yˆ

∂X2 1

< 0: the critical point is a maximum

• H > 0 and _∂X∂2Yˆ2

1 > 0: the critical point is a minimum

• H < 0 : the critical point is a saddle point

• H = 0 : no information

The coordinate of the critical point are obtained by solving the following system of two equations: ∂ ˆY ∂X1 = 0 and ∂ ˆY ∂X2 = 0 (A.11)

Bibliography

[1] Y. Cheng, G. Xu, D. Zhu, W. Zhu, and L. Luo, Thermal analysis for indirect liquid cooled multichip module using computational uid dynamic simulation and response surface methodology, Components and Packaging Technologies, IEEE Transactions on, vol. 29, no. 1, p. 39, Mar. 2006. [Online]. Available: http://dx.doi.org/10.1109/TCAPT.2006

[2] M. A. Bezerra, R. E. Santelli, E. P. Oliveira, L. S. Villar, and L. A. Escaleira, Response surface methodology (RSM) as a tool for optimization in analytical chemistry, Talanta, vol. 76, no. 5, p. 965, Sep. 2008. [Online]. Available: http: //dx.doi.org/10.1016/j.talanta.2008.05.019

[3] B. Zhou, Y. Li, J. Gillespie, G.-Q. He, R. Horsley, and P. Schwarz, Doehlert Matrix Design for Optimization of the Determination of Bound Deoxynivalenol in Barley Grain with Triuoroacetic Acid (TFA), Journal of Agricultural and Food Chemistry, vol. 55, no. 25, p. 10141, Nov. 2007. [Online]. Available: http://dx.doi.org/10.1021/jf0722957

[4] S. L. Ferreira, W. N. dos Santos, C. M. Quintella, B. B. Neto, and J. M. Bosque-Sendra, Doehlert matrix: a chemometric tool for analytical chemistry-review , Talanta, vol. 63, no. 4, p. 1061, Jul. 2004. [Online]. Available: http://dx.doi.org/10.1016/j.talanta.2004.01.015

Appendix B

Masks

•

Linear TLM structures

Mask name: FORME1-TLM

Layer 1: etch of alignment marks Layer 2: implantation

Layer 3: mesa etch

Layer 4: metal contacts lift-o

•

Inversion-mode MOSFETs and circular TLM structures

Mask name: FORME3 Mask1

Layer 1: etch of alignment marks / isolation Layer 2: S/D implantation

Layer 3: oxide etch for opening for S/D and body contacts Layer 4: oxide lift-o for gate pad

Mask name: FORME3 Mask2 Layer 5: S/D contacts lift-o

Layer 6: gate pad + body contact lift-o Layer 7: gate metal lift-o

Process Flow for Junctionless

MOSFETs with Raised Source and

Drain

Use mask: JLESS-INGAAS1(PO No 404-96284) 1. Litho level 0: ALIGN ETCH

• Standard S1813 process for wet etch

• Wet etch alignment marks InGaAs/InP (target depth ∼ 200 - 300 nm) with H₂SO₄:H₂O₂:DI (1:1:8) for ∼ 20 s

• PR removal with hot 1165 only (no plasmod)

2. Litho level1: GATE LIFTOFF (Note: This is for an etch) • Standard S1813 process for wet etch

• Digital wet etch of the InGaAs channel (16 - 20 nm deep) with cycles of dips in HCl:DI 1:10 (10 s) and dilute H2O2:DI 1:10 (10 s). Target: for 16 nm etch depth ->

20 cycles, for 20 nm etch depth -> 25 cycles. Ellipsometry model: In53Ga47As on InP Vladimir.

• PR removal with hot 1165 only (no plasmod)

3. Optimized surface passivation in 10% (NH4)2S for 30 min immediately followed by 8

nm ALD Al2O3

• Standard LOR3A/S1805 process for lifto

• 200 nm Pd evap, pre-evap heat to 100◦C for 30 min. Evap at 80◦C, evap rate: 0.5 Å/s for rst 50 nm then 1 Å/s.

5. Litho level2: OXIDE ETCH

• Standard S1813 process for wet etch

• BOE/DI (1/10) etch for 25 s to remove Al₂O₃ • PR removal with hot 1165 only (no plasmod) 6. Litho level3: S/D LIFTOFF

• Standard LOR3A/S1805 process for lifto • Pre-load heat 90◦C.

• Pre-deposition dip in ammonia/DI (1:10) for 20 s before loading • Deposit N-metal Au/Ge/Au/Ni/Au (14/14/14/11/200 nm) Standard litho processes:

• S1813 for etch : HMDS 4000 rpm for 60 s, S1813 4000 rpm for 60 s , bake 115◦C for 2 min, expose 7.5 s, develop MF319 for 45 s, oven bake 90◦_{C for 30 min}

• LOR3A/S1805 for lifto : HMDS 3000 rpm for 50 s, LOR3A 3000 rpm for 50 s, bake 150◦C for 3min, HMDS 3000 rpm for 50 s, S1805 3000 rpm for 50 s, bake 115◦_{C for 2 min, expose}

List of Achievements

•

Filed Patent Application

1. P. K. Hurley, K. Cherkaoui, V. Djara, Junctionless Nanowire Transistors for 3D Monolithic Integration of CMOS Inverters, European Patent Oce, Application no. 13162474.4 - 1555, led 05/04/13.

•

Accepted Publications

1. V. Djara, K. Cherkaoui, M. Schmidt, S. Monaghan, É. O'Connor, I. M. Povey,D. O'Connell, M. E. Pemble, and P. K. Hurley, Impact of Forming Gas Annealing on the Performance of Surface-Channel In0.53Ga0.47As MOSFETs With an ALD Al2O3

Gate Dielectric, IEEE Trans. Electron Devices, vol. 59, no. 4, p. 1084, 2012. 2. V. Djara, K. Cherkaoui, S. B. Newcomb, K. K. Thomas, E. Pelucchi, D. O'Connell,

L. Floyd, V. Dimastrodonato, L. O. Mereni, and P. K. Hurley, On the Activation of Implanted Silicon Ions in p-In0.53Ga0.47As, Semicond. Sci. Technol., vol. 27, no. 8,

p. 082001, 2012.

3. V. Djara, T. P. O'Regan, K. Cherkaoui, M. Schmidt, S. Monaghan, É. O'Connor, I. M. Povey, D. O'Connell, M. E. Pemble, and P. K. Hurley, Electrically Active Interface Defects in the In0.53Ga0.47As MOS system, Microelectron. Eng., vol. 109, p. 182,

2013.

4. M. A. Negara, V. Djara, T. P. O'Regan, K. Cherkaoui, M. Burke, Y. Y. Gomeniuk, M. Schmidt, É. O'Connor, I. M. Povey, A. J. Quinn, and P. K. Hurley, Investigation of Electron Mobility in Surface-Channel Al2O3/In0.53Ga0.47As MOSFETs, Solid-State

Electron., vol. 88, p. 37, 2013.

5. P. K. Hurley, É. O'Connor, V. Djara, S. Monaghan, I. M. Povey, R. D. Long, B. Sheehan, J. Lin, P. C. McIntyre, B. Brennan, R. M. Wallace, M. E. Pemble, and

K. Cherkaoui, The characterisation and passivation of xed oxide charges and interface states in the Al2O3/InGaAs MOS system, IEEE Trans. Device and Materials

Reliability (2013) - in press.

6. É. O'Connor, B. Brennan, V. Djara, K. Cherkaoui, S. Monaghan, S. B. Newcomb, R. Contreras, M. Milojevic, G. Hughes, M. E. Pemble, R. M. Wallace, and P. K. Hurley, A Systematic Study of (NH4)2S Passivation (22%, 10%, 5%, or 1%) on the

Interface Properties of the Al2O3/In0.53Ga0.47As/InP System for N-type and P-type

In0.53Ga0.47As Epitaxial Layers, J. Appl. Phys., vol. 109, no. 2, p. 024101-10, 2011

- This paper is in the top 20 most cited J. Appl. Phys. papers in 2012 . 7. K. Cherkaoui, V. Djara, É. O'Connor, J. Lin, M. A. Negara, I. M. Povey, S. Mon-

aghan, and Paul K. Hurley, Can Metal/Al2O3/In0.53Ga0.47As/InP MOSCAP Proper-

ties Translate to Metal/Al2O3/In0.53Ga0.47As/InP MOSFET Characteristics?, ECS

Transactions, vol. 45, no. 3, p. 79, 2012.

8. P. K. Hurley, R. D. Long, T. P. O'Regan, É. O'Connor, S. Monaghan, V. Djara, M. A. Negara, A. O'Mahony, I. M. Povey, A. Blake, R. Nagle, D. O'Connell, M. E. Pemble, and K. Cherkaoui, Equivalent Oxide Thickness Correction in the High- k/In0.53Ga0.47As/InP System, ECS Transactions, vol. 33, no. 3, p. 433, 2010.

9. A. O'Mahony, S. Monaghan, R. Chiodo, I. Povey, K. Cherkaoui, R. Nagle, É. O'Connor, R. Long, V. Djara, D. O'Connell, F. Crupi, M. E. Pemble, and P. K. Hurley, Struc- tural and Electrical Analysis of Thin Interface Control Layers of MgO or Al2O3 De-

posited by Atomic Layer Deposition and Incorporated at the High-k/III-V Interface of MO2/InxGa1-xAs (M = Hf|Zr, x = 0|0.53) Gate Stacks, ECS Transactions, vol.

33, no. 2, p. 69, 2010.

•

Oral Presentations at International Conferences

1. V. Djara, K. Cherkaoui, M. A. Negara, J. MacHale, M. Burke, É. O'Connor, I. M. Povey, D. O'Connell, M. E. Pemble, A. Quinn, and P. K. Hurley, Inversion-Charge Pumping Method for Mobility Extraction in Surface-Channel Al2O3/In0.53Ga0.47As

MOSFETs, IEEE Semiconductor Interface Specialists Conference (SISC), San Diego - United States, 2012.

2. V. Djara, K. Cherkaoui, M. Schmidt, Y. Y. Gomeniuk, É. O'Connor, I. M. Povey, D. O'Connell, S. Monaghan, M. E. Pemble, and P. K. Hurley, Study of Interface and Oxide Defects in High-k/In0.53Ga0.47As n-MOSFETs, IEEE Ultimate Integration on

Silicon (ULIS), Grenoble - France, 2012.

Pd/Al2O3/In0.53Ga0.47As MOSFETs, IEEE Semiconductor Interface Specialists Con-

ference (SISC), Arlington - United States, 2011.

4. V. Djara, K. Cherkaoui, K. K. Thomas, E. Pelucchi, D. O'Connell, L. Floyd, and P. K. Hurley , Annealing Investigations for High-k First N-channel In0.53Ga0.47As

MOSFET Development, IEEE Ultimate Integration on Silicon (ULIS), Cork - Ire- land, 2011.

5. V. Djara,K. Cherkaoui, K. K. Thomas, E. Pelucchi, D. O'Connell, L. Floyd, V. Dimastrodonato, L. O. Mereni, and P. K. Hurley, Anneal Process Optimization for Silicon Dopant Activation in Indium Gallium Arsenide Using a Doehlert Design of Experiment, European Materials Research Society (E-MRS), Strasbourg - France, 2010.

•

Poster Presentations at International Conferences

1. V. Djara, K. Cherkaoui, T. Lopez, É. O'Connor, I. M. Povey, K. K. Thomas, and P. K. Hurley, Junctionless InGaAs MOSFETs with InAlAs Barrier Isolation and Channel Thinning by Digital Wet Etching, IEEE Device Research Conference (DRC), Notre Dame - United States, 2013.

2. V. Djara, T. P. O'Regan, M. A. Negara, K. Cherkaoui, M. Burke, Y. Y. Gomeniuk, M. Schmidt, É. O'Connor, I. M. Povey, A. J. Quinn, and P. K. Hurley, Electron Mobility Degradation in Surface-Channel Al2O3/In0.53Ga0.47As MOSFETs, IEEE

Semiconductor Interface Specialists Conference (SISC), San Diego - United States, 2012.

•

Award

1. BOC Gases Ireland Postgraduate Bursary Award 2012 (runner up) for research ac- complishments in the eld of high-k/III-V metal-oxide-semiconductor eld-eect transistors (MOSFETs).

•

Publications in Preparation

1. V. Djara, K. Cherkaoui, M. A. Negara, M. Burke, J. MacHale, D. O'Connell, A. Quinn, and P. K. Hurley, Investigation of Border Traps and Mobility in Al2O3/In0.53Ga0.47As

MOSFETs Using Inversion-charge Pumping, IEEE Trans. Electron Devices.

2. V. Djara, K. Cherkaoui, T. Lopez, M. Burke, É. O'Connor, I. M. Povey, K. K.

Thomas, and P. K. Hurley, Impact of Channel Thickness in Junctionless Al2O3/In0.53Ga0.47As

•

Accepted Publications (Not Related to the PhD)

1. A. Wieczorek, V. Djara, F. H. Peters, J. O'Callaghan, K. K. Thomas, and B. Corbett, Inductively Coupled Plasma Deep Etching of InP/InGaAsP in Cl2/CH4/H2 Based

Chemistries With the Electrode at 20◦_{C, J. Vac. Sci. Technol. B, vol. 30, no. 5, p.}

051208, 2012.

2. É. O'Connor, V. Djara, S. Monaghan, P. K. Hurley, and K. Cherkaoui , Capacitance- Voltage and Interface State Density Characteristics of GaAs and In0.53Ga0.47As MOS

Capacitors Incorporating a PECVD Si3N4Dielectric, ECS Transactions, vol. 35, no.

3, p. 415, 2011.

3. S. Monaghan, K. Cherkaoui, É. O'Connor, V. Djara, P. K. Hurley, L. Oberbeck, E. Tois, L. Wilde, and S. Teichert , TiN/ZrO2/Ti/Al Metal-Insulator-Metal Capaci-

tors With Subnanometer CET Using ALD-Deposited ZrO2 for DRAM Applications,

IEEE Electron Device Lett., vol. 30, no. 3, p. 219, 2009.

4. M. Shayesteh, K. Huet, I. Toque-Tresonne, R. Negru, C. L. M. Daunt, N. Kelly, D. O'Connell, R. Yu, V. Djara, P. Carolan, N. Petkov, and R. Duy, Atomically-Flat Low-Resistive Germanide Contacts Formed By Laser Thermal Anneal, IEEE Trans. Electron Devices, vol. 60, no. 7, p. 2178, 2013.

5. M. Shayesteh, C. L. M. Daunt, D. O'Connell, V. Djara, M. White, B. Long, and R. Duy, NiGe Contacts and Junction Architectures for P and As Doped Germanium Devices, IEEE Trans. Electron Devices, vol. 58, no. 11, p. 3801, 2011.

6. R. A. Farrell, N. Petkov, M. T. Shaw, V. Djara, J. D. Holmes, and M. A. Mor- ris, Monitoring PMMA Elimination by Reactive Ion Etching from a Lamellar PS-b- PMMA Thin Film by ex-situ TEM Methods, Macromolecules, vol. 43, no. 20, p. 8651, 2010.

7. B. Toomey, K. Cherkaoui, S. Monaghan, V. Djara, É. O'Connor, D. O'Connell, L. Oberbeck, E. Tois, T. Blomberg, S. B. Newcomb, and P. K. Hurley, The Structural and Electrical Characterization of a HfErOx Dielectric for MIM Capacitor DRAM

Applications, Microelectron. Eng., vol. 94, p. 7, 2012.

8. Y. M. Georgiev, N. Petkov, B. McCarthy, R. Yu, V. Djara, D. O'Connell, O. Lotty, A. M. Nightingale, N. Thamsumet, J. C. deMello, A. Blake, S. Das, and J. D. Holmes, Fully CMOS-compatible top-down fabrication of sub-50 nm silicon nanowire sensing devices, Microelectron. Eng., 2014 (accepted).

9. M. Shayesteh, R. Duy, B. McCarthy, A. Blake, M. White, J. Scully, R. Yu, V. Djara, M. Schmidt, N. Petkov, and A.-M. Kelleher, Germanium Fin Structure Optimization

for Future MugFET and FinFET Applications, ECS Transactions, vol. 35, no. 2, p. 27, 2011.

10. R. Farrell, N. Kinahan, S. Hansel, K. Stuen, N. Petkov, M. Shaw, L. West, V. Djara, R. Dunne, O. Varona, P. Gleeson, S.-J. Jung, H.-Y. Kim, M. Kolesnik, T. Lutz, C. Murray, J. D. Holmes, P. Nealey, G. Duesberg, V. Krstic, and M. A. Morris, Large-Scale Parallel Arrays of Silicon Nanowires via Block Copolymer Directed Self- Assembly, Nanoscale, vol. 4, no. 10, p. 3228, 2012.

11. R. G. Hobbs, M. Schmidt, C. T. Bolger, Y. M. Georgiev, P. Fleming, M. A. Morris, N. Petkov, J. D. Holmes, F. Xiu, K. L. Wang, V. Djara, R. Yu, and J. P. Colinge, Resist-substrate Interface Tailoring for Generating High Density Arrays of Ge and Bi2Se3 Nanowires by Electron Beam Lithography, J. Vac. Sci. Technol. B, vol. 30,

In document Development of inversion-mode and junctionless Indium-Gallium-Arsenide MOSFETs (Page 185-194)