Coding Style: Best-Known Method for Synthesis
4.8 VERILOG OPERATORS
4.8.3 Shift Operator
Shift operations can be performed in Verilog by using the shift left operator for shifting a bus to the left or a shift right operator for shifting a bus to the right.
Example 4.19 shows a Verilog code that uses the shift left operator to shift the three-bit bus signal tempA by one bit to the left.
Example 4.19 Verilog Code Using the Shift Left Operator
module shift_left (inputA, inputB, outputA);
input [2:0] inputA, inputB;
output [2:0] outputA;
wire [2:0] outputA;
wire [2:0] tempA;
assign tempA = inputA & inputB;
assign outputA = tempA << 1;
endmodule
When the Verilog code of Example 4.19 is synthesized, the logic obtained is illustrated in Figure 4.18.
Example 4.20 shows the Verilog code for a test bench that can be used to simulate the Verilog code of module “shift_left” to verify that the logic obtained is as shown in Figure 4.18.
Example 4.20 Verilog Code for Test Bench to Simulate Module
“shift_left”
module shift_left_tb();
reg [2:0] reg_inputA, reg_inputB;
wire [2:0] wire_outputA;
integer i,j;
VERILOG OPERATORS 71
Declaration of inputA and inputB as three-bit input ports.
Shift left by one bit
initial begin
for (i=0; i<8; i=i+1) begin
// to force input stimulus for inputA reg_inputA = i;
for (j=0; j<8; j=j+1) begin
// to force input stimulus for inputB reg_inputB = j;
#10;
end end
end
shift_left shift_left_inst (.inputA(reg_inputA), .inputB(reg_inputB), .outputA(wire_outputA));
initial begin
$monitor ("inputA %b%b%b inputB %b%b%b tempA
%b%b%b outputA %b%b%b",reg_inputA[2], reg_inputA[1], reg_inputA[0], reg_inputB[2], reg_inputB[1],
inputA(1)
inputA(0) inputB(1)
inputB(0)
outputA(2)
outputA(1)
outputA(0)
outputA(2:0)
FIGURE 4.18. Diagram showing synthesized logic for module “shift_left.”
A for loop operation that allows a loop of i = 0 to i = 7
Instantiation of module shift_left
reg_inputB[0], shift_left_inst.tempA[2],
shift_left_inst.tempA[1], shift_left_inst.tempA[0], wire_outputA[2], wire_outputA[1], wire_outputA[0]);
end
endmodule
Example 4.21 shows the simulation results of the test bench module
“shift_left_tb”.
Example 4.21 Simulation Results of Test Bench Module “shift_left_tb”
inputA 000 inputB 000 tempA 000 outputA 000 inputA 000 inputB 001 tempA 000 outputA 000 inputA 000 inputB 010 tempA 000 outputA 000 inputA 000 inputB 011 tempA 000 outputA 000 inputA 000 inputB 100 tempA 000 outputA 000 inputA 000 inputB 101 tempA 000 outputA 000 inputA 000 inputB 110 tempA 000 outputA 000 inputA 000 inputB 111 tempA 000 outputA 000 inputA 001 inputB 000 tempA 000 outputA 000 inputA 001 inputB 001 tempA 001 outputA 010 inputA 001 inputB 010 tempA 000 outputA 000 inputA 001 inputB 011 tempA 001 outputA 010 inputA 001 inputB 100 tempA 000 outputA 000 inputA 001 inputB 101 tempA 001 outputA 010 inputA 001 inputB 110 tempA 000 outputA 000 inputA 001 inputB 111 tempA 001 outputA 010 inputA 010 inputB 000 tempA 000 outputA 000 inputA 010 inputB 001 tempA 000 outputA 000 inputA 010 inputB 010 tempA 010 outputA 100 inputA 010 inputB 011 tempA 010 outputA 100 inputA 010 inputB 100 tempA 000 outputA 000 inputA 010 inputB 101 tempA 000 outputA 000 inputA 010 inputB 110 tempA 010 outputA 100 inputA 010 inputB 111 tempA 010 outputA 100
VERILOG OPERATORS 73
$monitor is a Verilog system task that allows the monitoring of simulation results during simulation. The task would display the values of the specified signals during
simulation whenever the signal values change.
inputA 011 inputB 000 tempA 000 outputA 000 inputA 011 inputB 001 tempA 001 outputA 010 inputA 011 inputB 010 tempA 010 outputA 100 inputA 011 inputB 011 tempA 011 outputA 110 inputA 011 inputB 100 tempA 000 outputA 000 inputA 011 inputB 101 tempA 001 outputA 010 inputA 011 inputB 110 tempA 010 outputA 100 inputA 011 inputB 111 tempA 011 outputA 110 inputA 100 inputB 000 tempA 000 outputA 000 inputA 100 inputB 001 tempA 000 outputA 000 inputA 100 inputB 010 tempA 000 outputA 000 inputA 100 inputB 011 tempA 000 outputA 000 inputA 100 inputB 100 tempA 100 outputA 000 inputA 100 inputB 101 tempA 100 outputA 000 inputA 100 inputB 110 tempA 100 outputA 000 inputA 100 inputB 111 tempA 100 outputA 000 inputA 101 inputB 000 tempA 000 outputA 000 inputA 101 inputB 001 tempA 001 outputA 010 inputA 101 inputB 010 tempA 000 outputA 000 inputA 101 inputB 011 tempA 001 outputA 010 inputA 101 inputB 100 tempA 100 outputA 000 inputA 101 inputB 101 tempA 101 outputA 010 inputA 101 inputB 110 tempA 100 outputA 000 inputA 101 inputB 111 tempA 101 outputA 010 inputA 110 inputB 000 tempA 000 outputA 000 inputA 110 inputB 001 tempA 000 outputA 000 inputA 110 inputB 010 tempA 010 outputA 100 inputA 110 inputB 011 tempA 010 outputA 100 inputA 110 inputB 100 tempA 100 outputA 000 inputA 110 inputB 101 tempA 100 outputA 000 inputA 110 inputB 110 tempA 110 outputA 100 inputA 110 inputB 111 tempA 110 outputA 100 inputA 111 inputB 000 tempA 000 outputA 000 inputA 111 inputB 001 tempA 001 outputA 010 inputA 111 inputB 010 tempA 010 outputA 100 inputA 111 inputB 011 tempA 011 outputA 110 inputA 111 inputB 100 tempA 100 outputA 000 inputA 111 inputB 101 tempA 101 outputA 010 inputA 111 inputB 110 tempA 110 outputA 100 inputA 111 inputB 111 tempA 111 outputA 110
Note: Notice from the simulation results that the (LSB) is always a zero? This occurs because, when shifting left, the LSB is always tagged with logic zero. This causes the synthesized logic for module shift_left to have the outputA(0) grounded.
Example 4.22 shows a Verilog code that uses the shift right operator to shift the three-bit bus signal tempA by one bit to the right.
Example 4.22 Verilog Code Using the Shift Right Operator
module shift_right (inputA, inputB, outputA);
input [2:0] inputA, inputB;
output [2:0] outputA;
wire [2:0] outputA;
wire [2:0] tempA;
assign tempA = inputA & inputB;
assign outputA = tempA >> 1;
endmodule
When the Verilog code of Example 4.22 is synthesized, the logic obtained is illustrated in Figure 4.19.
VERILOG OPERATORS 75
Shift right by one bit
inputA(1)
inputA(2) inputB(1)
inputB(2)
outputA(0)
outputA(1)
outputA(2)
outputA(2:0)
FIGURE 4.19. Diagram showing synthesized logic for module “shift_right.”
Example 4.23 shows the Verilog code for a test bench that can be used to simulate the verilog code of module “shift_right” to verify that the logic obtained is as shown in Figure 4.19.
Example 4.23 Verilog Code for Test Bench to Simulate Module
“shift_right”
module shift_right_tb();
reg [2:0] reg_inputA, reg_inputB;
wire [2:0] wire_outputA;
integer i,j;
initial begin
for (i=0; i<8; i=i+1) begin
// to force input stimulus for inputA reg_inputA = i;
for (j=0; j<8; j=j+1) begin
// to force input stimulus for inputB reg_inputB = j;
#10;
end end
end
shift_right shift_right_inst (.inputA(reg_inputA), .inputB(reg_inputB), .outputA(wire_outputA));
initial begin
$monitor ("inputA %b%b%b inputB %b%b%b tempA
%b%b%b outputA %b%b%b",reg_inputA[2], reg_inputA[1], reg_inputA[0], reg_inputB[2], reg_inputB[1],
reg_inputB[0], shift_right_inst.tempA[2], shift_right_inst.tempA[1], shift_right_
inst.tempA[0], wire_outputA[2], wire_outputA[1], wire_outputA[0]);
end
endmodule
Example 4.24 shows the simulation results of the test bench module
“shift_right_tb.”
Example 4.24 Simulation Results of Verilog Test Bench Module
“shift_right_tb”
inputA 000 inputB 000 tempA 000 outputA 000 inputA 000 inputB 001 tempA 000 outputA 000 inputA 000 inputB 010 tempA 000 outputA 000 inputA 000 inputB 011 tempA 000 outputA 000 inputA 000 inputB 100 tempA 000 outputA 000 inputA 000 inputB 101 tempA 000 outputA 000 inputA 000 inputB 110 tempA 000 outputA 000 inputA 000 inputB 111 tempA 000 outputA 000 inputA 001 inputB 000 tempA 000 outputA 000 inputA 001 inputB 001 tempA 001 outputA 000 inputA 001 inputB 010 tempA 000 outputA 000 inputA 001 inputB 011 tempA 001 outputA 000 inputA 001 inputB 100 tempA 000 outputA 000 inputA 001 inputB 101 tempA 001 outputA 000 inputA 001 inputB 110 tempA 000 outputA 000 inputA 001 inputB 111 tempA 001 outputA 000 inputA 010 inputB 000 tempA 000 outputA 000 inputA 010 inputB 001 tempA 000 outputA 000 inputA 010 inputB 010 tempA 010 outputA 001 inputA 010 inputB 011 tempA 010 outputA 001 inputA 010 inputB 100 tempA 000 outputA 000 inputA 010 inputB 101 tempA 000 outputA 000 inputA 010 inputB 110 tempA 010 outputA 001 inputA 010 inputB 111 tempA 010 outputA 001 inputA 011 inputB 000 tempA 000 outputA 000 inputA 011 inputB 001 tempA 001 outputA 000 inputA 011 inputB 010 tempA 010 outputA 001 inputA 011 inputB 011 tempA 011 outputA 001 inputA 011 inputB 100 tempA 000 outputA 000 inputA 011 inputB 101 tempA 001 outputA 000 inputA 011 inputB 110 tempA 010 outputA 001 inputA 011 inputB 111 tempA 011 outputA 001 inputA 100 inputB 000 tempA 000 outputA 000 inputA 100 inputB 001 tempA 000 outputA 000 inputA 100 inputB 010 tempA 000 outputA 000 inputA 100 inputB 011 tempA 000 outputA 000 inputA 100 inputB 100 tempA 100 outputA 010 inputA 100 inputB 101 tempA 100 outputA 010 inputA 100 inputB 110 tempA 100 outputA 010
VERILOG OPERATORS 77
inputA 100 inputB 111 tempA 100 outputA 010 inputA 101 inputB 000 tempA 000 outputA 000 inputA 101 inputB 001 tempA 001 outputA 000 inputA 101 inputB 010 tempA 000 outputA 000 inputA 101 inputB 011 tempA 001 outputA 000 inputA 101 inputB 100 tempA 100 outputA 010 inputA 101 inputB 101 tempA 101 outputA 010 inputA 101 inputB 110 tempA 100 outputA 010 inputA 101 inputB 111 tempA 101 outputA 010 inputA 110 inputB 000 tempA 000 outputA 000 inputA 110 inputB 001 tempA 000 outputA 000 inputA 110 inputB 010 tempA 010 outputA 001 inputA 110 inputB 011 tempA 010 outputA 001 inputA 110 inputB 100 tempA 100 outputA 010 inputA 110 inputB 101 tempA 100 outputA 010 inputA 110 inputB 110 tempA 110 outputA 011 inputA 110 inputB 111 tempA 110 outputA 011 inputA 111 inputB 000 tempA 000 outputA 000 inputA 111 inputB 001 tempA 001 outputA 000 inputA 111 inputB 010 tempA 010 outputA 001 inputA 111 inputB 011 tempA 011 outputA 001 inputA 111 inputB 100 tempA 100 outputA 010 inputA 111 inputB 101 tempA 101 outputA 010 inputA 111 inputB 110 tempA 110 outputA 011 inputA 111 inputB 111 tempA 111 outputA 011
Note: Notice from the simulation results that the (MSB) is always a zero?
This occurs because when shifting right, the MSB is always tagged with logic zero. This causes the synthesized logic for module shift_right to have the outputA(2) grounded.