19. Oscillators
20.1. smaRTClock Interface
The smaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-face registers are located on the CIP-51’s SFR map and provide access to the smaRTClock internal regis-ters listed in Table 20.1. The smaRTClock internal regisregis-ters can only be accessed indirectly through the smaRTClock Interface.
20.1.1. smaRTClock Lock and Key Functions
The smaRTClock Interface is protected with a lock and key function. The smaRTClock Lock and Key Reg-ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restric-tions, but the key codes must be written in order. If the key codes are written out of order, the wrong codes are written, or an invalid read or write is attempted, further writes and reads to RTC0ADR and RTC0DAT will be disabled until the next system reset. Once the smaRTClock interface is unlocked, software may per-form accesses of the smaRTClock registers until an invalid access, the interface is locked, or a system reset.
Reading the RTC0KEY register at any time will provide the smaRTClock Interface status and will not inter-fere with the sequence that is being written. The RTC0KEY register description in SFR Definition 20.1 lists the definition of each status code.
20.1.2. Using RTC0ADR and RTC0DAT to Access smaRTClock Internal Registers
The smaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The RTC0ADR register selects the smaRTClock internal register that will be targeted by subsequent reads or writes. Prior to each read or write, BUSY (RTC0ADR.7) should be checked to make sure the smaRTClock Interface is not busy performing another read or write operation. A smaRTClock Write operation is initiated by writing to the RTC0DAT register. Below is an example of writing to a smaRTClock internal register.
Step 1. Poll BUSY (RTC0ADR.7) until it returns a ‘0’.
Step 2. Write 0x06 to RTC0ADR. This selects the internal RTC0CN register at smaRTClock Address 0x06.
Step 3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
An smaRTClock Read operation is initiated by setting the smaRTClock Interface Busy bit. This transfers the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in RTC0DAT until the next read or write operation. Below is an example of reading a smaRTClock internal register.
Step 1. Poll BUSY (RTC0ADR.7) until it returns a ‘0’.
Step 2. Write 0x06 to RTC0ADR. This selects the internal RTC0CN register at smaRTClock Address 0x06.
Step 3. Write ‘1’ to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
Step 4. Poll BUSY (RTC0ADR.7) until it returns a ‘0’.
Step 5. Read data from RTC0DAT. This data is a copy of the RTC0CN register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
ning of each series of consecutive reads. Software must check if the smaRTClock Interface is busy prior to reading RTC0DAT. Autoread is enabled by setting AUTORD (RTC0ADR.6) to logic 1.
20.1.4. RTC0ADR Autoincrement Feature
For ease of reading and writing the 48-bit CAPTURE and ALARM values, RTC0ADR automatically incre-ments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting an alarm or reading the current smaRTClock timer value.
Table 20.1. smaRTClock Internal Registers
smaRTClock Address
smaRTClock Register
Register Name Description
0x00 - 0x05 CAPTUREn smaRTClock Capture Registers
Six Registers used for setting the 47-bit smaRTClock timer or reading its current value. The LSB of CAPTURE0 is not used.
0x06 RTC0CN smaRTClock Control Register
Controls the operation of the smaRTClock State Machine.
0x07 RTC0XCN smaRTClock Oscillator Control Register
Controls the operation of the smaRTClock Oscillator.
0x08–0x0D ALARMn smaRTClock Alarm Registers
Six registers used to set or read the 47-bit smaRTClock alarm value. The LSB of ALARM0 is not used.
0x0E RAMADDR smaRTClock Backup RAM Indirect Address Register
Used as an index to the 64 byte smaRTClock backup RAM.
0x0F RAMDATA smaRTClock Backup RAM Indirect Data Register
Used to read or write the byte pointed to by RAMADDR.
SFR Definition 20.1. RTC0KEY: smaRTClock Lock and Key
Bits 7–0: RTC0STATE. smaRTClock State Bits Read:
0x00: smaRTClock Interface is locked.
0x01: smaRTClock Interface is locked. First key code (0xA5) has been written, waiting for second key code.
0x02: smaRTClock Interface is unlocked. First and second key codes (0xA5, 0xF1) have been written.
0x03: smaRTClock Interface is disabled until the next system reset.
Write:
When RTC0STATE = 0x00 (locked), writing 0xA5 followed by 0xF1 unlocks the smaRTClock Interface.
When RTC0STATE = 0x01 (waiting for second key code), writing any value other than the second key code (0xF1) will change RTC0STATE to 0x03 and disable the smaRTClock Interface until the next system reset.
When RTC0STATE = 0x02 (unlocked), any write to RTC0KEY will lock the smaRTClock Interface.
When RTC0STATE = 0x03 (disabled), writes to RTC0KEY have no effect.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:0xAE
SFR Definition 20.2. RTC0ADR: smaRTClock Address
Bit 7: BUSY: smaRTClock Interface Busy bit.
Writing a ‘1’ to this bit initiates a smaRTClock indirect read operation. This bit is automati-cally cleared by hardware when the operation is complete.
0: smaRTClock Interface is not busy.
1: smaRTClock Interface is busy performing a read or write operation.
Bit 6: AUTORD: smaRTClock Interface Auto Read Enable.
0: BUSY must be written manually for each smaRTClock indirect read operation.
1: The next smaRTClock indirect read operation is initiated when RTC0DAT is read by soft-ware.
Bit 5: VREGEN: Backup Supply Voltage Regulator Enable.
This bit is automatically set to 1b when VRTC-BACKUP > VDD.
0: Backup Supply Voltage Regulator Disabled (smaRTClock powered from VDD).
1: Force Backup Supply Voltage Regulator Enabled (smaRTClock powered from V RTC-BACKUP).
Bit 4: SHORT: Short Read/Write Timing Enable.
0: smaRTClock reads and writes are 4 system clocks wide.
1: smaRTClock reads and writes are 1 system clock wide.
Note: Increasing the speed of the smaRTClock reads and writes may also slightly increase power consumption.
Bits 3–0: RTC0ADDR: smaRTClock Address Bits
These bits select the smaRTClock internal register that is targeted by reads/writes to RTC0DAT.
Note: The RTC0ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn internal register.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
BUSY AUTORD VREGEN SHORT RTC0ADDR Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:0xAC