2.7 PUF Emulation PDL Evaluation
2.7.4 Stability
Ideally, any pair of configuration bits ci, cj (ci 6= cj) should produce a pair of delays with a non-zero delay difference when applied to two PDLs, and the delay difference should remain stable. However, this is not always true in reality. PDL is a timing-based scheme. Thus, it is sensitive to environmental changes. Also, the environmental impact on delays may not be equal for each path inside the PDL. Non-uniform impact on delays thus leads to instability in pairwise delay differences.
As an example, Figure 2.6 illustrates two possible outcomes of temperature variations for two PDL paths. Figure 2.6a shows a scenario where path 2 is more sensitive to temperature than path 1. At lower temperature t1, the delay on PDL path 1 dt1P ath1 is larger than the delay on PDL path 2 dt1
P ath2 (∆d1 = dt1P ath1− dt1P ath2 > 0). However, when the temperature increases to t2, delay on path 2 increases at a faster rate, and at a point the delay on path 2 is greater than the delay on path 1 (∆d2 = dt2P ath1− dt2P ath2 < 0). We intend to avoid this
Temperature Δd1 Δd2 Path 1 Path 2 t1 t2 (a) Scenario 1 Temperature Δd3 Δd4 Path 3 Path 4 t1 t2 (b) Scenario 2
Figure 2.6: Signal propagation delay of PDL vs. temperature of two PDL paths scenario because this type of instability results in sign inversion of delay differences, creating a significant error with a relatively large probability. Figure 2.6b shows an almost ideal scenario where the sign of delay differences between path 3 and path 4 (∆d3 and ∆d4) does not change as the temperature varies from t1 to t2. Also, ∆d3 ≈ ∆d4, which means that the delay difference value stays relatively stable as well. Stable delay difference, in turn, leads to low error rate in emulation results.
Similar to PUFs, PDL is primarily affected by temperature and voltage. To analyze how PDL behaviors can vary, we test PDL in different environmental settings. Our experimental results show that PDL is capable of producing relatively stable delay differences in normal conditions. All delay measurements are done on a chain of four PDLs using the delay characterization circuit. The PDL chain is connected serially as shown in Figure 2.7. All delays are measured from the signal-in port to the signal-out port.
PDL
1PDL
2PDL
3PDL
4 Configuration [19:15] Configuration [14:10] Configuration [9:5] Configuration [4:0] Signal-in Signal-out2.7.4.1 Temperature
We evaluate the delays of PDL for 20,000 different configuration bits on a chain of four PDLs at five different temperatures within the allowed operating temperature range (0 ∼ 85◦C). The delays are measured using the delay characterization circuit as described in Figure 2.4. We adjust the temperature by placing the FPGA device in a temperature controlled chamber. To evaluate the delay characteristic variations as core temperature changes, we first collected delay measurements for 10,000 PDLs on FPGA. Then, we observe the stability of PDL in different temperatures through constructing 10,000 delay pairs (reference temperature vs. tested temperature) and calculate the delay ratio between each pair. Ideally, if the temperature impact on the PDL chain is uniform over all PDL paths, we should observe those delay ratios stay unchanged as we adjust the temperature. We set the delay ratios measured at 25◦C as our reference and compare all delay ratios at different temperatures with it.
Figure 2.8: Delay characteristic variation under different temperature settings.
Figure 2.8 indicates the delay characteristic changes as core temperature varies. The average delay slightly decreases by 6.89%, while the variance in delays increases by 4.25% as temperature increase from 5◦C to 85◦C.
(a) Delay pair ratios 25◦C vs. 5◦C.
(b) Delay pair ratios 25◦C vs. 45◦C.
(c) Delay pair ratios 25◦C vs. 65◦C.
(d) Delay pair ratios 25◦C vs. 85◦C.
Figure 2.9: Delay ratio stability over 4 different temperature settings, VCCINT fixed at 1.2V. Red line: linear regression result. Green line: degree-2 quadratic regression result. 45◦C, 65◦C and 85◦C. Each blue point represents a specific delay ratio between two config- uration vectors, where the x coordinate is the ratio calculated in the reference temperature and the y coordinate is the ratio calculated in the test temperature. The black line in each subgraph indicates the result of a perfectly stable PDL. Linear regression (red line) and degree-2 quadratic regression (green line) were performed on the collected data. The degree-2 quadratic regressions in all four settings are very close to straight lines, indicating a linear relationship between the x-axis and the y-axis. To quantify the stability of PDL in all temperature settings, we evaluate the slope, intercept, and standard error of all linear regression results in Table 2.4.
In general, at 5◦C and 45◦C, the regression slope is very close to 1, the intercept is close to 0, and the standard error is almost negligible, meaning the impact of temperature change
Temperature Slope Intercept std err
5◦C 0.9795 0.0200 0.0027
45◦C 0.9813 0.0186 0.0030
65◦C 0.6304 0.3696 0.0075
85◦C 0.4450 0.5550 0.0093
Table 2.4: Linear regression results on PDL temperature stability evaluation.
is mostly uniform over all PDL paths so that the delay difference stays relatively stable. At higher temperatures 65◦C and 85◦C, the regression slopes are respectively 0.6304 and 0.4450, far from 1, indicating some paths are much more sensitive to the temperatures than others. This result means at very high temperature the PDL-based emulation segment result has a much higher probability of being inconsistent with the results collected at 25◦C. In our emulation platform design, we assume that the temperature varies at most 20◦C from the room temperature. Thus, it is safe to claim that PDL is stable against reasonable thermal fluctuation.
2.7.4.2 Voltage
Similar to the evaluation of thermal variations, we investigate the voltage variation impact on PDL. Our experimental platform Spartan-6 does not contain a freely tunable DC-DC converter in the power module, thus adjusting core voltage cannot be done internally. More- over, the manufacturer of our experimental platform has a fairly stringent requirement on FPGA core voltage (VCCINT = 1.2V), making it very difficult and risky to directly apply an adjustable external power source to the FPGA core. Fortunately, Spartan-6 provides an extended performance mode that applies to VCCINT = 1.26V. We first evaluate the changes in delay characteristics as we change the VCCINT in Figure 2.10. We observe that the av- erage delay slightly decreases by 11.19%, while the variance in delays decreases by 19.46% as VCCINT increase from 1.2V to 1.26V.
We also evaluate the delay ratio between 10,000 PDL delay pairs in both normal mode and extended performance mode. The result is shown in Figure 2.11.
Figure 2.10: Delay characteristic variation under two VCCINT settings.
Figure 2.11: Delay ratio stability when increasing FPGA core voltage from 1.2V to 1.26V, operating temperature fixed to 25◦C. Red line shows linear regression result, green line shows degree-2 quadratic regression result.
pact on each path is relatively stable and consistent. Also, both linear and degree-2 quadratic regression were performed and the results are plotted in the figure. The quadratic regression result (green line) is almost flat, indicating that a linear model is a better representation of the data. The linear regression result (red line) indicates that the delay pair ratios stay mostly stable as we increase the voltage. Linear regression has a slope of 0.9754, intercept of
0.02463, and standard error of 0.0027, very close to the ideal result (black line). Based on the results, we claim it is safe to assume that the PDL delay ratio stays relatively stable against minor changes in voltage and the impact of voltage variation is uniform over all paths.
Also, it is interesting to notice that less variance is observed on both ends of the plot. This phenomenon is also observed in temperature variation experiments. When the delay ratios are further away from 1, meaning the delay differences are larger, the PDL is less likely to behave differently when the environment changes.