Statistical Model

Since the sign-bit is in the non-speculative timing group, it is not affected by timing violations and hence timing-errors are ideally distributed around a zero

mean, i.e.

. (4.5)

4.4.2 Statistical Model

In order to develop a useful statistical model for the timing-error noise

characteristics, some additional system variables are introduced to describe the

frequency and size of errors. The probability of a finite error, i.e. , is given by . The target error rate of the DVS loop regulates by controlling the circuit supply voltage. An ideal control loop is assumed, with infinite supply voltage

modulation bandwidth, such that determines the probability of sub-critical voltage scaling in a given clock cycle.

Figure 4.12: Bit transition probabilities for a 16-bit sinewave representation of four frequencies. Normalised frequencies are annotated in radians per second.

The relationship between , and is non-linear and time-varying due to

dynamic PVT effects. The distribution of bit errors in a word determines the average

overall error magnitude. The distribution is dependent on both the path activation

probability and the path length for each bit position in an -bit word.

The probability of logic transitions at individual bit positions depends on the

underlying signal statistics. The probability of a bit transition between consecutive

samples is assumed to be given by a single activity factor, . Figure 4.12 shows the probability of a bit transition, , over a 16-bit word between consecutive samples of sine waves of various frequencies. Noticeably, there are two distinct regions, one

where toggling tends to and one due entirely to sign extension where . The cut-off between these regions is determined by the signal bandwidth, where for all but very narrowband applications, or for , is roughly independent of signal bandwidth across LSBs. Hence, the assumption that is equal for each of LSBs can be made.

Finally, the influence of the path lengths on the bit error distribution is

delay statistics, a simplification is introduced that the th

LSB is the only bit that

fails. This allows us to accurately model the error noise without needing to know

relative delays for all bits (this information is of course not known at the algorithm

design stage). Although at very low error rates (the intended operating point) the th

LSB is likely to be the only bit that will fail (as it has by definition greater fan-in

than the lower order LSBs), as the error rate increases, other bits in the LSB group

will start to fail, which then introduces an error term into the analysis. This is not

considered significant as long as the error rate is low enough.

The probability mass function of is given diagrammatically in Figure 4.13, with error variance, , given by

(4.6)

Assuming the signal is a uniformly distributed integer with variance , the signal to error noise ( ) ratio, which determines the useful dynamic range, is given by

(4.7)

Figure 4.14 shows (7) against for and , along with simulation results, for a 16-bit adder. Clearly the model is an excellent fit with the simulation

results until the MSB group fails at high error rates (well beyond the intended

operating point). Simulation results of a conventional 16-bit adder with only a single

timing constraint are also plotted to illustrate the proposed approach. Figure 4.15,

plotted on a logarithmic axis shows how both curves tend to ~96 dB dynamic range

at . There are only very few simulation points at low error rates as very long simulation runtime is required to reach low error rates.

Figure 4.13: Probability mass function of .

Figure 4.14: Theory vs. simulations for 16-bit PDS and conventional adders.

Figure 4.15: Theory vs. simulations for 16-bit PDS adders.

2M-1 - 2M-1 0 pe / 2 1 – pe pe / 2 - 2N-1 2N-1

In order to analyze the accumulation of timing-error noise in a system

composed of multiple PDS stages, a simple linear-noise model is used in order to

ascertain its effect at the output, in a similar fashion to the analysis of rounding

errors [59]. Starting with a model of infinite precision, an external error input is

added for each register bank that contains RFFs on critical paths. It is assumed that

only these end-points are subject to sub-critical timing violations and that sufficient

DVS loop bandwidth exists to vary the operating point in response to a non-zero

timing-error rate, before setup timing on the remaining non-critical end-points are

violated.

Next, our analysis is extended by generalising to a pipeline of repeated

identical stages which are considered over samples. The timing-error noise for the

th

datapath stage is given as . The non-linear timing-error noise is modelled in a linear fashion given the following assumptions:

1. is an additive, independent, identically distributed (i.i.d.) white-noise process with assumed zero-mean.

2. is a wide-sense stationary random process, i.e. mean and co-variance are independent of time index .

3. is assumed to be uncorrelated to all other signals, such as input signals and other noise signals.

Over datapath stages, the average noise power is

(4.8)

and the signal to error noise ratio at the output becomes