Superimposed Reconfiguration Controller

The Superimposed Reconfiguration Controller (SRC) has been extended from [88].

It has been designed in order to control the fault mitigation process. It is a repro-grammable hardware/software co-design that can be easily extended to support different fault detection techniques. In the core functionality of the SRC there is an optimized state machine for microreconfiguration [88]. The depth of its FIFO is long enough to store multiple frames that define configuration of one LUT. This results in an improved reconfiguration speed. It is also light weight and hence power efficient compared to HWICAP. The SRC provides fault monitoring, detec-tion, injection and correcdetec-tion, by rapidly reading and writing specific frames in the FPGA configuration system.

5.5.4.1 Architecture

The SRC has an ICAP state machine and it is connected with a bidirectional In-put buffer, two asynchronous connections to the OutIn-put buffer and to the ICAPE2 Macro. The architecture is similar to MiCAP, however the Input Buffer contains a wider variety of commands and the state machine allows fault injection and fault tolerance processes. The Input buffer is an asynchronous FIFO buffer that holds the ICAP read, write and reliability commands along with specialized configu-ration data which are to be written into the configuconfigu-ration memory. All the data read from the configuration memory via the ICAP is stored in the output buffer.

Once the data is ready, the processor has to read the frames from the output buffer.

Using this element the commands and data can be read or written into the FPGA configuration memory with the ICAP module. This is depicted in Figure 5.8.

The SRC is a fully synchronous design using the src clk as the single clock.

All elements are synchronous to the rising edge of this clock. As a result, all in-terfaces are also synchronous to the rising edge of this clock. The SEU correction interface and the fault injection interface use the microscrubbing functionality en-abled by the SRC interface to monitor and correct SEUs, by reading modifying and writing back frames. When the SRC is in the IDLE state, the ability of the controller to detect and correct errors is suspended. If it detects an input from the

ICAPE2 clk

CSIB I[31:0]

RDWRB

O[31:0]

SRC state machine

Input Buffer

Output Buffer

Din[31:0] wren rden Dout[31:0]

Dout[31:0] rden wren Din[31:0]

SRC_enSRC_seu_enMiCAP_rdSRC_done

Figure 5.8: Details of the SRC architecture

user to inject errors into the configuration memory, the fault injection interface provides a specific location and commands the controller to create a bit flip into the configuration memory via microreconfiguration.

5.5.4.2 State Machine

The SRC’s state machine has additional states compared to MiCAP that are de-signed to improve the reliability of the design. Additionally to the Read and Write state, the SRC has the SEU and FI state. The SEU en state, is the state that is activated if a SEU has occurred. The FI en state, is the state that is activated if the system needs to undergo fault injection.

The SRC State machine contains various states that orchestrate the controller’s read and write activity and mitigation processes. The state machine handles the multiplexing of data between the frames of the input buffer and the commands of

the ICAP, from the single port RAM to establish the reconfiguration process. The state machine contains three major states: a wait state, a read state and a write state.

In the Wait state the SRCs state machine waits until all the data (frames + ICAP commands) are filled into the input FIFO.

In the Read state,

1. SRC en MiCAP rd is set to high 2. RDWRB is set to high

3. CSIB is set to low so ICAP primitive is enabled

4. The read command in the input buffer is fetched and written to the ICAPs input port. The command is written in the rising edge of the clock.

5. Once the read command is sent, the ICAP starts fetching the configuration data. The frames fetched from the ICAP are written into the output buffer.

6. CSIB is set to high so the ICAP is disabled 7. SRC done is set to high

In the Write state,

1. SRC en is set to high and MiCAP rd is set to low 2. RDWRB is set to low

3. CSIB is set to low so the ICAP primitive is enabled

4. The write command is fetched from the input buffer and the command is written to the ICAP’s input port. The command is written in the rising edge of the clock.

5. Once the write command is sent, the ICAP knows that next incoming data is the configuration data that has to be written into the configuration memory of the FPGA. Now the state machine reads the data from the input buffer and writes the data into the ICAP input port. The ICAP continues to write the data sent from the input buffer into the configuration memory until the input buffer is empty.

6. CSIB is set to high so the ICAP is disabled 7. SRC done is set to high

The fault injection state in the state machine is a process were the reconfigu-ration controller after reading the data, reverses them, creating a bitflip. Therefore the 0 becomes 1 and vice versa. Therefore, in the Fault Injection state,

1. SRC en and SRC SEU en is set to high and MiCAP rd is set to low 2. RDWRB is set to low

3. CSIB is set to low so the ICAP primitive is enabled

4. The write command is fetched from the input buffer and the command is written to the ICAP’s input port. The command is written on the rising edge of the clock.

5. Once the write command is sent, the ICAP knows that next incoming data is the configuration data that has to be written into the configuration memory of the FPGA. Now the state machine reads the data from the input buffer and writes the data into the ICAP input port based on the stuck-at fault (0 or 1).

6. CSIB is set to high so the ICAP is disabled 7. SRC done is set to high

One more state added in the state machine is the SEU state. Here, if this state is enabled, the data are under SEU and they are scrubbed. Hence, in the SEU state,

1. SRC en, SRC SEU en MiCAP rd are set to high 2. RDWRB is set to high

3. CSIB is set to low so the ICAP primitive is enabled

4. The read command in the input buffer is fetched and written to the ICAPs input port. The command is written in the rising edge of the clock.

5. Once the read command is sent, the ICAP starts fetching the configuration data. The frames fetched from the ICAP are written into the output buffer.

6. RDWRB is set to low 7. MiCAP rd is set to low

8. The write command is fetched from the input buffer and the command is written to the ICAP’s input port.

9. Once the write command is sent, the ICAP knows that next incoming data is the configuration data that has to be written into the configuration memory of the FPGA. Now the state machine reads the data from the input buffer, inverses the data and writes the inversed data into the ICAP input port. The ICAP continues to write the data sent from the input buffer into the config-uration memory until the input buffer is empty.

10. CSIB is set to high so ICAP disabled

11. SRC done is set to high

12. SRC SEU en is set to low, so the reliability aspect is disabled.