System in Package Technology

There has not been a generally accepted definition for system in package (SIP). Prof. R.

R. Tummala proposed that system-level packaging can be divided into two categories: SIP and SOP.^[3] That is, SIP is commonly referred to as two or more chips stacked on a single packaging substrate, which are then packaged with molding compounds and interconnected during the process of packaging. On the other had SOP may be considered the system-on-a-PCB or system-on-a-substrate, incorporating multiple chips and discrete components on a miniaturized circuit board and featuring the implementation of various system components with thin layer techniques.

In this chapter, SIP is regarded as a heterogeneous integration, including chips or modules stacked vertically to realize a three-dimentional structure; and embedded digital, RF, and optical components; and the system integrated into a miniaturized packaging system. For simplicity, let us define SIP as (multi-) functional systems built up using semiconductors and other technologies in the electronic package dimension via heterogeneous integration. SIP focuses on achieving the highest value for a single packaged microsystem. Its concept applies to quite diverse technology and application areas, ranging from sensors and actuators, RF modules for mobile communication devices, to solid-state lighting, and even health care devices, such as biosensors.

To distinguish between various SIPs, one can categorize SIP into three categories, as shown in Table 8.1.^[5] SIP level 1 refers to packages with multidies, such as MCM, PiP, and PoP. SIP level 2 refers to subsystems built up using more than just the IC process, such as passive integration. The highest level, SIP level 3 refers to submicrosystems and microsystems with more than electric functions, built up using multitechnologies, such as SOP^[3]and a miniature camera.

Table 8.1 SIP classification

More than... ... one IC ... IC process ...electronics

SIP level 1, e.g., MCM

SIP level 2, e.g., passive integration

SIP level 3, e.g., MEMS

Generally, the SOC and SIP technologies can be complementary, not competing, ap-proaches to achieve customer value. They are synergistic in nature, wherein SOC can be a component of SIP. The decision on which approach to use (or how to partition when both approaches are possible) is based on a thorough assessment of development and manufac-turing costs and a realistic assessment of the market for the product. Rather than arguing about which is better, one should try to take into consideration the capabilities and their intrinsic advantages.

8.3 System in Package Technology 153

8.3.2 SIP Technology

Various companies and research institutes have designed a large variety of SIP implemen-tations, with some pursuing the minimal package footprint, and some aiming at the minimal stacking profiles. The mainstream techniques include the following:

(1) Wire-bonding stacking integration, which has been used by early memory chips stack-ing SIP, has been applied to integration of the hybrid SIP of logic and memory chips. Al-though the wire bonding is a mature technology in the microelectronic packaging industry, it must face the challenges that come with SIP. One of the major drawbacks of the adoption of wire bonding is the significant increase of the wiring density of a packaged system containing multi-input/multi-output logic chips. As the number of layers to be stacked in SIPs con-tinues to increase, wire bonding with various height differences is required. Consequently, while thinning down chips in SIP to a minimum, people use inverse wire bonding, i.e., they first finish the bonding on the substrate, and then implement the wire bonding on the chips.

(2) The second technique is the combination of flip-chip and wire bonding. Compared with wire bonding techniques, flip-chip can take full advantage of the die area to offer more interconnections and enhance system performance by shortening the interconnections to the system. Indeed, the complexity of SIP is also raised. On the one hand, it needs to support the flip-chip process, and on the other hand, substrate technologies with smaller feature sizes are required for high-density interconnections. The focus of the next generation of chip stacking techniques will be the connection of electrodes.^[6]

(3) The third technique is package on package stacking, i.e., the replacement of chips by packaged bodies, as shown in Figure 8.4. Polyimide ribbons may be used as a flexible carrier.

While acting as a thin substrate, they can be folded over to provide a mounting surface for a second overstacked layer; or rigid substrate may be used. The most significant advantages of this method are the ability to guarantee the yields by testing the individual packaged modules separately, with each module containing one or more chips. Other advantages include the overall size reduction enabled by higher wiring density on substrates, high-density

(a) Schematic diagram of whole PoP module

(b) Top view of the sample (c) Bottom view of the sample

Figure 8.4 Schematic of package on package stacking (Courtesy of ASTRI, Hong Kong)

154 Chapter 8 System-level Packaging Technology interconnection between packaged modules through the pin arrays, and the ability to provide a variety of packaged modules to accommodate user’s requirements. The major difficulty lies in the selection of foldable substrate and interconnection on the folding edges.

(4) Substrate based integration techniques for SIP^[7−15] have been studied to meet the needs of some massive applications. They include a wide variety of design and fabrication technologies, for the incorporation of sensors, RF modules, memory modules, and embedded processors with DRAM.

A traditional microsystem package takes double roles: first to provide inputs and outputs for integrated chips, and second to provide interconnections for the active and passive devices on a system circuit board.

What we are looking for is the implementation of multiple system functions in an en-vironment that is low mass, low profile, low cost, and high performance. The design of such a system may demand high performance digital logic, memory, radio frequency, and analog signal and broadband optical performance. It does not demand a compromise in performance, since the individual technologies are incorporated discretely. In addition, the complexity of system design and the time requirement are reduced, so the testing becomes easier.

Generally, this system integration technology is an advanced system-level packaging tech-nology, involving the whole set of system functions and interconnections. In a sense, it assimilates merits of SOC, MCM, 3D-stacking, etc., to accomplish system integration on the highest system level and in the most cost effective way. A typical sample was imple-mented by the Georgia Institute of Technology, which shows the first integration example of optical, RF, and digital functionalities in a single module^[8] intended for the broadband application of a smart network switcher.

(5) Through silicon via (TSV) has been widely accepted as the one of the techniques enabling the effective and highly dense three-dimensional integration of hetero- or homo-geneous ICs and micromachined functional structures, such as sensors, actuators, and an-tennas, in a package. This type of vertical interconnection may provide a short and low-resistance/impedance interlayer signal path for these stacked chips or modules, so that the relatively high signal loss, temporal delay, and noise pickup associated with the long inter-connections in the in-plane integration methodologies can be mostly eliminated. In addition, TSV may provide the flexibility in 3D interconnection wiring and layout for both digital and RF/microwave circuitry.

Currently, two generic approaches for 3D SIP fabrication are used, i.e., “vias first” and

“vias last” approach. In the “vias first” approach, the TSV is formed before the standardized fabrication processing of IC wafers. In the “vias last” approach vias are formed after the IC is fabricated. The “via last” approach is selected in this work, since no harmful impurities (from the IC process point of view) are introduced, and the process is relatively simple.

However, precise control of post-IC process temperature and careful selection of etching agents are needed for the integrity of the IC fabricated.

The integration of the 3D SIP based on TSV involves several important processing steps:

formation of vias; deposition of via insulation, barrier, and seed layer; via filling; wafer thinning; wafer stacking; and so on, as shown in Figure 8.5.

The formation, i.e., the drilling, of the vias is one of the critical process steps for the success in the TSV microfabrication. Among the technical options, the deep reactive ion etching (DRIE) is considered to be the ideal one for batch drilling of deep vias into Si substrates.

In order to insulate the subsequent via metal from the surrounding silicon, SiO2 is de-posited by plasma enhanced chemical vapor deposition. Ideally, coverage over the entire via structure should be conformal. However, the relatively high aspect ratio of the via can pose a

8.3 System in Package Technology 155

(a) Vias drilling (b) Vias filling (c) Wafer thinning

(d) Wafer stacking (e) Product

Figure 8.5 A key process flow for TSV SIP

problem requiring careful optimization of deposition parameters. It is also critical to con-trol stress in the insulating layer, in order to ensure structural integrity under subsequent processing and operating conditions. The titanium-tungsten (TiW) barrier and the Cu seed layer are deposited by magnetic sputtering. There are two methods of copper electroplat-ing. One is DC plating, the other is periodic pulse reverse (PPR) current platelectroplat-ing. In TSV’s copper electroplating, cupric ions are reduced to copper and deposited on the cathode, but the deposition rate is different between the top of the via and the bottom of it. Because the depletion rate of cupric ions is faster than the diffusion rate of cupric ions from the bulk solution into the bottom of vias, the concentration of cupric ions at the entrance of vias is higher than that at the bottom. This concentration gradient leads to different deposition rates: the deposition rate at the top is faster than that at the bottom. Eventually, voids or seams are usually formed inside of vias. In the case of DC plating, there was only one nucle-ation step, and copper grains grow continuously with electroplating time, since it provides a continuous current with a constant current density and the via is always kept at the cathode potential. So, it is difficult to obtained defect-free copper filling for vias by DC plating.

The next step is wafer thinning. The packages of products such as mobile phones are thinner and thinner. The maximum thickness required is currently 1.2 mm, and the thickness of packages of some products has even reached 1.0 mm. As the number of stacked chips increases, the thickness of chips must decrease. There are three main methods for thinning chips—mechanical grinding, chemical etching, and atmosphere downstream plasma (ADP).

The mechanical grinding method can usually reduce the thickness to about 150μm, while the plasma etching method can reduce the thickness to 50–100μm. A method for reducing the thickness to 10–30 μm is being developed. In addition, handling thinner wafers with thicknesses smaller than 50μm is also a big problem. A glass carrier wafer is often used to temporarily bond the device wafer in the postthinning processes. ^[16]

Wafer bonding or wafer stacking is a key process to form a 3D structure by attaching chip-to-chip (C2C), using metallic bonding, dielectric bonding, or metallic/dielectric hybrid bonding. Metallic bonding with low-temperature solder and metallic bonding with Cu-Cu thermal compression are widely used. Wafers or chips can be connected face-to-face (F2F) or face-to-back (F2B). Memory stacks tend to use F2B stacking, while memory-logic prefers F2F stacking. ^[16]

In addition to the manufacturing technique issues, it is critical to select an integration approach as well, especially to decide whether a complete chip stacking or a packaged module stacking architecture should be used. SIP based on packaged module stacking has a more appealing manufacturing cost. Alternatively, a pure chip stacking can be more advantageous, if the yield of individual chips is high enough, as shown in Figure 8.6. In fact, the SIP methodologies in practice can be flexible and diversified and can be a combination of various integration techniques.

156 Chapter 8 System-level Packaging Technology

Chip stacking

Packaged body stacking Qualified rate of chip

Relative cost

Figure 8.6 Manufacturing cost vs. integration methods

Currently, stacking technology faces three major challenges. The first lies in microint-erconnection. With the shrinking of package and the increase in the number of chip in-put/output ports, the method used to construct the interconnection between a very large numbers of pins with extremely fine pitch becomes crucial. The relevant SIP package sub-strate needs to carry ultrafine wiring, and more refined layer-up subsub-strate has to be built to accommodate the requirements of higher speed and density. The second challenge is stacking chips. SIP technology can provide stacking up to nine layers, e.g., the packaged five-chip stack-up from Renesas Technology has a profile of 1.5 mm, with a 1 mm packaged profile targeted for its next generation stacking SIP with over 10 layers. However, with the increase in the number of stacked layers, how to build the stacking with thinner dies and to guarantee the reliability becomes quite a concern. At the same time, carrying out efficient heat dissipation and cooling is required. A particularly severe problem is how to test the tier up to ensure the proper operation of chips and the yield of SIP products. The third challenge is the adaptation to the SIP design environment. Currently, the design software environ-ments for SIP relatively fall behind and demand improvement and enhancement based on the inherent design resources. In particular, as the march into high-frequency bands has increased the ratio between line length and wavelength more and more, more sophisticated distribution parametric models should be to replace used the traditional lumped model in analysis and design; in addition, new issues will arise from the adoption of SIP, such as the electromagnetic radiation coming along with the high-speed signal transmission. In order to realize a genuinely global optimization, efforts on these issues are indispensable.

8.3.3 Comparison between System-on-chip and System-in-package

As we have mentioned previously, diversified integration methodologies, such as System-on-chip(SOC), SIP, and System-System-on-chip(SOC), each has advantages and disadvantages, and one can find their respective role in real applications. Furthermore, during the process of continuous development and advancement, breakthroughs in one technology can alter an applications status quo. Based on the current technology, we can discuss preliminarily the advantages and disadvantages of these system integration methods.

When choosing a system integration mode, people need to consider a specific product design from the point of view of product features, development cycles and market scale. In terms of the integration of heterogeneous devices, SIP can conveniently realize the integration of analog and logic circuits, CMOS and SiGe, LSI, and various passives. From the cost and profit point of view, SOC is advantageous for large volume production, and SIP is advantageous for small volume production. From the reuse of resources, SIP may incorporate off-the-shelf chips, SOC can reuse existing IP; however, as a whole, SOC design is more sophisticated and difficult. From the design point of view, SOC design is made from a specific technology library, and SIP may reduce the number of components and the size and layout complexity of PCB; however since there is a lack of research on corresponding design fundamentals, in many cases, vendors have to do the technical research themselves.

8.4 RF System Package Technology 157