System Setup

ensures that the return currents always travel as near as possible to their corresponding trace. Signals in adjacent layers were routed perpendicularly, so that the horizontal and vertical layers alternate. This significantly limited the crosstalk between signal traces of adjacent layers.

Impedance mismatch of transmission line on PCB can cause signal reflection prob-lems, especially in high frequency environments. The impedance of 50Ω for single-ended signals and the impedance of 100Ω for differential signals were chosen for approximate matching with signal drivers and signals on off-board components. The trace widths of the single-ended signals were adjusted for each layer in order to maintain constant transmission line impedance across different layers. Series resistor terminations have been used on long traces to attenuate the signal reflections. All differential signal trace pairs were routed together with fixed spacing. PCB layer thicknesses and trace widths were chosen to ensure uniform impedance value throughout the board as shown in Figure 3.26.

High speed signals, such as the data and address buses of the ZBTSRAMs, DSP EMIF signals and the clocks were routed with matched lengths to ensure consistent signal delay, which is important for all high speed synchronous designs.

Ground bounce is another problem due to high switching activities on the high pin-count FPGA and DSPs. In extreme cases, the voltage drop can be significant enough to make the on-board ICs momentarily malfunction and produce errors [CKRB03].

Therefore, as many as possible bypassing capacitors should be provided to ensure proper system operation. There are over 500 bypassing capacitors placed on PowerEye with capacitance values ranging from 22pF to 680µF.

3.6. System Setup

As described in the previous sections, the implemented hardware system features a very flexible architecture that can be easily scaled up. Depending on the requirements, three different setups can be utilized for various optical tracking applications.

3.6.1. 3-Camera System

The basic setup is a 3-Camera system shown in Figure 3.27, where three cameras configured in the CameraLink Base mode are connected to PowerEye via the CLinkRx-TripleBase grabber board.

On PowerEye, three image data streams are fed simultaneously to the FPGA, where the feature point extraction takes place. The 2D feature point coordinates are calculated by the FPGA for each camera in parallel. The results are then sent to one or both DSPs, which are responsible for correspondence matching and 3D reconstruction that require low computational cost but highly complex math and control operations. A host, such as a laptop, can access PowerEye via the standard Gigabit Ethernet or USB

Figure 3.27.: 3-camera system

2.0 interface to initialize the cameras, visualize the 3D tracking data and perform the overall system control at runtime.

3.6.2. 6-Camera System

It is easy to extend the 3-camera system to a 6-camera system by cascading two Pow-erEye boards via the high-speed LVDS link, as illustrated in Figure 3.28.

Figure 3.28.: 6-camera system

In this system, the two PowerEye boards can work in a Master-Slave fashion. The FPGAs of both master and slave PowerEye calculate the 2D feature point positions for each camera independently as in the 3-camera system. The slave FPGA (FPGA on

3.6. System Setup 53

the slave PowerEye) sends its local results to the master FPGA, where the 2D feature point information from all the 6 cameras are collected. One of the master DSPs is responsible for establishing the feature point correspondence across the cameras, while the second master DSP remains free for the final 3D reconstruction.

It is obvious that the inter-board communication is an important issue that can influence the overall system performance. As discussed in Section 3.5.7, the LVDS link provides enough data transfer bandwidth for exchanging 2D feature point information between master and slave PowerEye. It even allows real-time raw image data to be transmitted from one PowerEye to another.

3.6.3. Many-Camera System

For applications that require even more cameras, it is possible to build a networked many-camera system using the Gigabit Ethernet interface available on PowerEye. Fig-ure 3.29 illustrates an architectural diagram.

Figure 3.29.: Many-camera system

In such a system, every three cameras are grouped together and connected to a Pow-erEye board, forming a processing node. The FPGA and DSPs on each PowPow-erEye board perform the 2D image analysis and calculate the feature point positions in images cap-tured by the local cameras. The results are then sent to a central processor or a server over Ethernet. The server can be a standard PC, which integrates the 2D information from various processing nodes and estimates the 3D position and orientation of the targets to be tracked. Interconnecting processing nodes with the server can be easily achieved using standard Ethernet switches. Since the 2D object information consumes very little bandwidth of Gigabit Ethernet, we can scale to large numbers of cameras to cover a large tracking volume.

One of the most challenging problems in an optical tracking system with a large number of cameras is camera synchronization. When tracing moving objects, we must ensure that the images are captured at exactly the same moment in time. If the images from various cameras are captured at different moments, corresponding feature points from different views may not represent the same point in space. This will in turn lead to significant amount of error in the final 3D reconstruction step. Thus, it is a reasonable requirement to have strictly time-synchronized cameras to guarantee correct tracking results. The problem of camera synchronization becomes non-trivial as the number of cameras increases. In this thesis, an efficient solution to this problem is presented.

More details are explained in Section 5.3.4.

3.7. Summary

In this chapter, the hardware design for the proposed optical tracking system is de-scribed. The complete hardware system is divided into three sub-systems : the high-speed camera, the CameraLink grabber and the PowerEye image processing system.

The camera features a modular architecture, allowing to easily adapt with various im-age sensors and interfaces. The currently used MT9M413 CMOS sensor is able to output 500 images per second at the resolution of 1280 × 1024. The camera integrates a low-cost FPGA for sensor control and communication with the outside world. Cam-eraLink was chosen as the camera interface to transmit large amounts of pixel data in real-time. Two different CameraLink grabbers have been developed, which can be used to interface three CameraLink BASE cameras and one CameraLink Full camera respectively. The PowerEye image processing system takes advantages of both FPGA and DSP to perform complex image processing algorithms at high frame rate. A Cam-eraLink Simulator capable of simulating the behavior of three cameras simultaneously was implemented for simplifying the system verification. The flexible hardware archi-tecture allows to construct a highly scalable optical tracking system.