Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels.

Separate procedures are described for each level.

Assembly Code Example

WDT_off:

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; reset WDT WDR

; Write logical one to WDCE and WDE in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16

15.5.1 Safety Level 1 (WDTON Fuse Unprogrammed)

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer and/or changing the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.

15.5.2 Safety Level 2 (WDTON Fuse Programmed)

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

15.6 Register Description

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15.6.1 MCUCSR – MCU Control and Status Register Name:  MCUCSR

Offset:  0x34 [ID-000004d0]

Reset:  0x00

Property:  When addressing I/O Registers as data space the offset address is 0x54

The MCU Control and Status Register provides information on which reset source caused an MCU Reset.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

.

Bit 7 6 5 4 3 2 1 0

WDRF BORF EXTRF PORF

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 3 – WDRF Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 2 – BORF Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 1 – EXTRF External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 0 – PORF Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

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15.6.2 WDTCR – Watchdog Timer Control Register

Name:  WDTCR

Offset:  0x21 [ID-000004d0]

Reset:  0x00

Property:  When addressing I/O Registers as data space the offset address is 0x41

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

Bit 7 6 5 4 3 2 1 0

WDCE WDE WDPn[2:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 4 – WDCE Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See Code Examples.

Bit 3 – WDE Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

Bits 2:0 – WDPn[2:0] Watchdog Timer Prescaler 2, 1, and 0 [n = 2:0]

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in the table below.

Table 15-1. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles

0 0 0 16K (16,384) 17.1ms 16.3ms

0 0 1 32K (32,768) 34.3ms 32.5ms

0 1 0 64K (65,536) 68.5ms 65ms

0 1 1 128K (131,072) 0.14s 0.13s

1 0 0 256K (262,144) 0.27s 0.26s

1 0 1 512K (524,288) 0.55s 0.52s

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WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles

Typical Time-out at V_CC = 3.0V

Typical Time-out at V_CC = 5.0V

1 1 0 1,024K (1,048,576) 1.1s 1.0s

1 1 1 2,048K (2,097,152) 2.2s 2.1s

System Control and Reset