TITLE
OPTIMIZATION AND DEVELOPMENT OF A LOW POWER MICROCONTROLLER FOR IOT APPLICATION
IVAN CHONG WEI YANG
This Report is Submitted in Partial Fulfilment of Requirements for The Bachelor Degree of Electronic Engineering (Telecommunication Electronic) with Honours
Faculty of Electronic and Computer Engineering Universiti Teknikal Malaysia Melaka
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DEDICATION
Dedicated to my beloved family members and friends, your love and support are the
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ACKNOWLEDGEMENT
First and foremost, I would like to express my deepest gratitude towards my supervisor Dr. Wong Yan Chiew. For she has showed much patience and guidance along my journey of this final year project. There would not be this project if without her as my supervisor.
Moreover, technical support from Mr. Sree. He has help me with my tools and project development solution when problems are faced in the design and software.
Nevertheless, unconditional love and support that are received from all my beloved family members and friends. It is what given me strength that keep me away from giving up this project.
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ABSTRACT
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ABSTRAK
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TABLE OF CONTENT
CONTENT Pages
TITLE ... i
STATUS VERIFICATION FORM ... ii
STUDENT DECLARATION ... iii
SUPERVISOR DECLARATION ... iv
DEDICATION ... v
ACKNOWLEDGEMENT ... vi
ABSTRACT ... vii
ABSTRAK ... viii
TABLE OF CONTENT ... ix
LIST OF TABLES ... xiv
LIST OF FIGURES ... xvi
LIST OF ABBREVIATIONS ... xix
CHAPTER 1 ... 1
INTRODUCTION ... 1
1.1 Project Overview ... 1
1.2 Problem Statements ... 1
1.3 Objectives ... 2
1.4 Scope of Project ... 2
1.5 Chapter Organization ... 3
CHAPTER 2 ... 4
LITERATURE REVIEW ... 4
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2.1.1 Terminology ... 5
2.1.2 Advanced High-performance Bus (AHB) ... 5
2.1.3 Advanced System Bus (ASB) ... 6
2.1.4 Advanced Peripheral Bus (APB) ... 7
2.1.5 Advanced eXtensible Interface (AXI) ... 7
2.2 I2C ... 7
2.2.1 DW_apb_i2c ... 8
2.2.2 DW_apb_i2c features: ... 8
2.2.3 DW_apb_i2c block diagram ... 9
2.3 Clock Gating ... 10
2.3.1 The review of clock gating technique ... 11
2.4 Conclusion ... 13
CHAPTER 3 ... 14
METHODOLOGY ... 14
3.1 Project Flow ... 15
3.2 Design process flow ... 16
3.3 Conclusion ... 17
CHAPTER 4 ... 18
DEVELOPMENT OF FINITE STATE MACHINE ... 18
4.1 Introduction of Finite State Machine ... 18
4.2 Accelerometer ... 18
4.2.1 Accelerometer specification ... 19
4.2.2 Falling behaviour ... 19
4.3 Flow Chart of Finite State Machine ... 21
4.4 VCS result ... 24
4.5 DC result ... 25
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4.5.2 DC Timing report ... 27
4.6 ICC result ... 28
4.6.1 ICC Power report ... 29
4.6.2 ICC Timing result ... 30
4.6.3 ICC layout physical dimension ... 31
4.7 Comparison of DC and ICC... 32
4.7.1 Power report comparison ... 33
4.7.2 Timing report comparison ... 34
4.8 Discussion ... 35
4.9 Conclusion ... 37
CHAPTER 5 ... 38
CLOCK GATING TECHNIQUE FOR POWER OPTIMIZATION IN EMBEDDED SYSTEM ... 38
5.1 Introduction ... 38
5.2 DC result ... 39
5.2.1 Schematic ... 39
5.2.2 Power report ... 42
5.2.3 Timing report ... 42
5.3 ICC result ... 43
5.3.1 Layout diagram ... 43
5.3.2 Power report ... 44
5.3.3 Timing report ... 45
5.3.4 Layout dimension ... 46
5.4 Comparison with and without clock gating technique... 47
5.4.1 DC result comparison ... 47
5.4.2 ICC result comparison ... 54
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5.6 Conclusion ... 59
CHAPTER 6 ... 60
DEVELOPMENT WITH RANDOM ACCESS MEMORY (RAM) ... 60
6.1 Introduction of RAM ... 60
6.2 Design specification ... 60
6.3 Development and result ... 62
6.3.1 VCS design and result ... 62
6.3.2 DC design and result ... 64
6.3.3 ICC design and result ... 67
6.4 Comparison of design between with and without RAM module ... 69
6.4.1 VCS comparison ... 69
6.4.2 DC comparison ... 72
6.4.3 ICC comparison ... 76
6.5 Comparison between with and without Clock gating technique ... 78
6.5.1 DC comparison ... 78
6.5.2 ICC comparison ... 81
6.6 Benchmarking ... 83
6.7 Discussion ... 84
6.8 Conclusion ... 86
CHAPTER 7 ... 87
CONCLUSION ... 87
7.1 Conclusion ... 87
7.2 Recommendation ... 88
Bibliography ... 89
APPENDIX I ... 92
APPENDIX II ... 93
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APPENDIX IV ... 101
APPENDIX V ... 103
APPENDIX VI ... 106
APPENDIX VII ... 114
APPENDIX VIII ... 120
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LIST OF TABLES
CONTENT Pages
Table 2-1 result of efficiency of clock gating technique... 12
Table 2-2 the power report of the result with and without clock gating logic ... 13
Table 4-1 accelerometer specification ... 19
Table 4-2 data of power report ... 26
Table 4-3 data of timing report ... 27
Table 4-4 data from ICC power report ... 29
Table 4-5 data from ICC timing report ... 30
Table 4-6 DC and ICC data power report ... 33
Table 4-7 DC and ICC data timing report ... 34
Table 5-1 power data from DC with clock gating... 42
Table 5-2 Timing data from DC with clock gating ... 42
Table 5-3 power data from ICC with clock gating ... 44
Table 5-4 timing data of ICC with clock gating ... 45
Table 5-5 DC power comparison ... 51
Table 5-6 DC timing comparison ... 53
Table 5-7 IC layout physical dimension comparison ... 54
Table 5-8 ICC power comparison ... 55
Table 5-9 ICC timing comparison... 56
Table 6-1 IoT application design specification ... 60
Table 6-2 DC power report with RAM ... 66
Table 6-3 timing report with RAM ... 67
Table 6-4 ICC power report with RAM ... 68
Table 6-5 ICC timing report with RAM ... 69
Table 6-6 DC power report comparison ... 75
Table 6-7 DC timing report comparison ... 75
Table 6-8 IC layout dimension comparison ... 76
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Table 6-10 ICC timing report comparison ... 77
Table 6-11 DC power comparison ... 80
Table 6-12 DC timing comparison ... 81
Table 6-13 IC layout dimension comparison ... 82
Table 6-14 ICC power comparison ... 82
Table 6-15 ICC timing comparison... 83
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LIST OF FIGURES
CONTENT Pages
Figure 2-1 Block Diagram of DW_apb_i2c ... 9
Figure 2-2 example of clock gating circuit ... 12
Figure 2-3 clock gating circuit principle diagram ... 13
Figure 3-1 project flow... 15
Figure 3-2 Process flow ... 16
Figure 4-1 falling pattern by accelerometer ... 20
Figure 4-2 flow chart of the finite state machine ... 22
Figure 4-3 schematic view of RTL module ... 24
Figure 4-4 waveform of the RTL ... 24
Figure 4-5 schematic view of the module ... 25
Figure 4-6 gate level schematic view inside the module ... 26
Figure 4-7 graph of power report ... 27
Figure 4-8 slack vs clock period ... 28
Figure 4-9 ICC layout ... 29
Figure 4-10 ICC power consumption vs clock period ... 30
Figure 4-11 ICC slack vs clock period ... 31
Figure 4-12 ICC layout dimension ... 32
Figure 4-13 power consumption vs clock period of DC and ICC... 33
Figure 4-14 slack vs clock period of DC and ICC ... 35
Figure 5-1 clock gating cell... 39
Figure 5-2 DC schematic module ... 40
Figure 5-3 expansion of the module... 40
Figure 5-4 DC clock gating cell ... 41
Figure 5-5 clock gating cell ENCLK ... 41
Figure 5-6 power consumption vs clock gating DC with clock gating ... 42
Figure 5-7 slack against clock period of DC with clock gating ... 43
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Figure 5-9 power consumption vs clock period of ICC with clock gating ... 45
Figure 5-10 slack vs clock period of ICC with clock gating ... 46
Figure 5-11 IC physicla layout dimension with clock gating ... 47
Figure 5-12 schemactic view of DC without clock gating technique ... 48
Figure 5-13 expansion of the cock line without clock gating technique... 48
Figure 5-14 schematic view of DC with clock gating technique ... 49
Figure 5-15 clock gating cell... 50
Figure 5-16 the connection of ENCLK produced by clock gating cell... 50
Figure 5-17 DC power comparison ... 52
Figure 5-18 DC timing comparison ... 53
Figure 5-19 IC layout dimension comparison between wihout clock gating (a) and with clock gating (b) ... 54
Figure 5-20 ICC power comparison ... 56
Figure 5-21 ICC timing comparison ... 57
Figure 6-1 Calculation for RAM size 1536 bits ... 61
Figure 6-2 Calculation for new uploading rate ... 62
Figure 6-3 RTL schematic diagram ... 63
Figure 6-4 finite state machine (u2) module waveform ... 63
Figure 6-5 RAM (u1) module waveform ... 64
Figure 6-6 DC schematic result... 64
Figure 6-7 finite state machine (u2) module ... 65
Figure 6-8 DC schematic of finite state machine (top left) and RAM (right) ... 66
Figure 6-9 IC layout with RAM ... 68
Figure 6-10 RTL schematic without RAM ... 69
Figure 6-11 RTL waveform without RAM ... 70
Figure 6-12 RTL schematic with RAM ... 70
Figure 6-13 RTL (u2) waveform with RAM ... 71
Figure 6-14 RTL (u3) waveform ... 71
Figure 6-15 DC schematic without RAM ... 72
Figure 6-16 DC schematic expansion without RAM ... 72
Figure 6-17 DC shematic with RAM ... 73
Figure 6-18 DC schematic expansion with RAM ... 74
Figure 6-19 IC layout comparison between without RAM (a) and with RAM (b) ... 76
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LIST OF ABBREVIATIONS
IoT Internet of Things RTL Register Transfer Level
IC Integrated Circuit DC Design Compiler
VCS Verification Compiler Simulator ICC Integrated Circuit Compiler
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CHAPTER 1
INTRODUCTION
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In this chapter, explanation of the details is done regarding the project optimization
and development of a low power microcontroller for IoT applications. This chapter
includes project background, problem statement, objectives, scope of project and chapter organization.
1.1 Project Overview
IoT is the new enhancement or application of microcontroller technology. Forecasting in the year of 2020, everything from home cities will have IoT devices installed at surroundings. Huge number of IoT devices are expected, power consumption will be the essential consideration in designing microcontroller. The main objective of this project is to achieve the power consumption of microwatts in simulation design of the microcontroller for IoT application. Clock gating technique will be implemented to reduce the power consumption of the microcontroller. The simulation design will be conducted in Synopsys platform with Verilog language and no hardware prototype will be produced. The result of this project is the design system that can achieve a low power consumption in microwatts.
1.2 Problem Statements
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IoT devices most likely using battery as their power source. Due to the convenient and miniature size of the IoT devices, the battery size would be small as well. Thus, the battery lifespan will be considerably short. To overcome this battery problem, a low power consumption of microcontroller is needed for IoT applications. One of solution in designing a low power consumption microcontroller is by implementing a technique called “clock gating”. This clock gating technique will reduce the power consumption of the devices. It is implemented while designing the RTL for the microcontroller embedded system.
1.3 Objectives
There are five objectives which need to be focused in this project and achieved at the end of it.
i. To develop a low power microcontroller specifically for IoT applications ii. To optimize the power consumption of the microcontroller using Synopsys
tool and clock gating technique
iii. To achieve a low power microcontroller embedded system design for IoT application.
1.4 Scope of Project
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1.5 Chapter Organization
This thesis comprises of seven chapters:
Chapter 1 is explaining the introduction of the project. This comprises project background, objectives, problem statement, scopes of project, and chapter organization.
Chapter 2 is explaining the theory that is related to this project, AMBA, I2C, and clock gating technique.
Chapter 3 is the illustration of process flow of this project in detail explanation. This also includes the tools of Synopsys software that are used in this project.
Chapter 4 is the development process of finite state machine. It explain the model structure, flow chart and all development stages using VCS, DC and ICC tools.
Chapter 5 discuss about the power optimization clock gating technique. The effectiveness of the technique is analysed.
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CHAPTER 2
LITERATURE REVIEW
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In this chapter, books, journals, and article are being discussed in relation to this project. Advanced Microcontroller Bus Architecture (AMBA), I2C bus and clock gating technique are discussed in related to the project of developing low power microcontroller for IoT application.
2.1 AMBA
Advanced microcontroller bus architecture in short AMBA for ARM. AMBA define the specification for on-chip communication standard[2]. All embedded system design must be designed according to the AMBA standard.
AMBA ver 2.0 consists of three different buses:
i. Advanced High-performance Bus (AHB) ii. Advanced System Bus (ASB)
iii. Advanced Peripheral Bus (APB)
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2.1.1 Terminology
The terms that describe the operation of Bus:
i. Bus cycle – it is a unit that represent one bus clock period. AHB and APB define bus clock period start from a rising edge to rising edge transitions. ASB define different which is from falling edge to falling edge transition.
ii. Bus transfer – it can be either a read or write operation of a data object. AHB and ASB may require one or more bus cycle and terminated by a completion command from the addressed slave. But APB always requires two bus cycle for a bus transfer operation.
iii. Burst operation – it is define as one or more data transaction been initiated by the bus master that consist of equal width of transaction to the increase of the address space region. But this burst operation only apply for AHB and ASB, not APB.
2.1.2 Advanced High-performance Bus (AHB)
AMBA AHB are design in to support high performance and high clock frequency. AHB do comes with some features:
i. Burst transfers ii. Split transactions
iii. Single-cycle bus master handover iv. Single-clock edge operation
v. Non-tristate implementation
vi. Wider data bus configurations (64/128 bits)
Most commonly applications of AHB is direct memory access (DMA) and digital signal processing (DSP).
AMBA AHB system design contains four components:
