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Advancing System-Level Analysis and

Design of Specialized Architectures

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Citation

Xi, Likun. 2018. Advancing System-Level Analysis and Design of

Specialized Architectures. Doctoral dissertation, Harvard University,

Graduate School of Arts & Sciences.

Citable link

http://nrs.harvard.edu/urn-3:HUL.InstRepos:41121197

Terms of Use

This article was downloaded from Harvard University’s DASH

repository, and is made available under the terms and conditions

applicable to Other Posted Material, as set forth at

http://

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LSU

VSU

L2

ISU

IFU

(38)
(39)

IFU

ISU

LSU

FXU

VSU

0.0

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vsx astargcc2k6 libquantummcf 2

k6 perlben

ch

omnetppbwavescalcucactlixusADM dealII gemsFD

TD lbm povraysoplex

gcc2k vprmcf2k art mesa swim 0 1 2 3 4 5 6 7 Nor maliz ed po w er

(43)

IFU

ISU

LSU

FXU

VSU

0

1

2

3

4

5

6

7

8

Nor

maliz

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area

(44)

0

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(45)

I-cache

Branch

target

buffer

Branch

predictor

buffer

Inst.

Decoder

I-TLB

(46)

0

2

I-cache

0

1

Branch

target

buffer

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Branch

predictor

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Inst.

buffer

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Decoder

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(47)

Unified

issue queue

completion table

Global

renaming

Register

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area

MR0

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table

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(48)

D-cache

Load reorder

queue

Store reorder

queue

D-TLB

(49)

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reorder

queue

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reorder

queue

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General-purpose registers

Fixed-point ALU

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(51)

Vector register file

Floating-point ALU

0

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register

file

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MR2

DPM

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64

(54)

gcc

mcf

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+

.

.

(61)

IFU

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ov

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nce

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LSU

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0.3

0.4

0.5

0.6

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Ratio

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4

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L2 Cache

CPU0

L1 Cache

System bus

MC

DRAM

DRAM

Lane

0 La ne 1 La ne 2 La ne 3 BUF0 BUF1 ARR0 ARR1 ARR2 ARR3

STR0 STR1 La ne 4 La ne 5 La ne 6 La ne 7 SPAD/DMA interface ACCEL1 MEM

CPU1

L1 Cache

Scratchpad accelerator

DMA

Transfer descriptors CHAN 0 CHAN 3 SRC ADDR DEST ADDR LENGTH SRC ADDR DEST ADDR LENGTH SRC ADDR DEST ADDR LENGTH SRC ADDR DEST ADDR LENGTH Channel selection ACCEL0 MEM La ne 0 La ne 1 La ne 2 La ne 3 L1 Cache TLB Cache controller

Design Parameter Values

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i = 16

to 31

A[32:

A[48:63

i = 0

N

15]

A[0:15]

A[16:31]

i = 0

to 15

Begin DMA of A as soon as the first flush chunk completes.

+ Pipelined

DMA

Break up flush and DMA into page sized chunks

i = 0

N

+ DMA-triggered

compute

Begin loop iteration 0 as soon as A[0] arrives.

A[32:47]

A[16:31]

Ready bits track data at granularity G

(for illustration purposes G = 16)

Copy array

via DMA

Flush array from

CPU caches

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PE0 PE1 PE2 PE3 B0

B4 B5 B6 B1 B2 B3

B7 Input Scratchpad PE4 PE5 PE6 PE7 B0

B4 B5 B6 B1 B2 B3

B7 Weight Scratchpad B0 Output Scratchpad B1 B2 B3 B4 B5 B6 B7 + + + + + + + + Contr ol Logic CPU0 CPU1

L1 $ L1 $

2MB L2 $

LPDDR4 MC 4GB LPDDR4 System Bus ACP IO Interface DMA

8 MACC Arrays

16 16 32 16 4GB LPDDR4 ISP ACC complex CPU2 CPU3

L1 $ L1 $

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×

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Model config file

+ parameters

(Weights/inputs)

FC

Preprocessing

Quantization

Compression

Blocking / Tiling

Data layout

Hardware description file

(target backend, SoC

interface, kernel selection,

SRAM size, etc)

Tiling optimizer (per layer)

CONV

FC

Other

Runtime scheduler

Optimized CPU

code

NVDLA

(107)

×

×

(108)

×

×

=

/

(

)

×

×

=

(

,

)

=

/

(

)

=

/

(

)

(109)

Input feature maps

Output feature maps

B

o

Kernels

C

B

o

H

B

i

W

W

H

M

K

r

K

c

C

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64KB

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6

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×

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10

1

10

2

10

3

10

4

10

5

PDlloF GurDtion (FyFles)

0

10

20

30

40

50

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(

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(129)

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size class

Sample

allocation?

Do sampled allocation

Get free

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Allocate pages

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empty?

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Is small

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10

1

10

2

10

3

10

4

10

5

PDlloF GurDtion (FyFles)

(132)

0

5

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15

20

25

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0

10

20

30

40

50

60

tFPDlloF tiPe iPprovePent (%)

(148)

0

10

20

30

40

50

60

PDlloF() tiPe iPprovePent (%)

(149)
(150)

10

0

10

1

10

2

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3

10

4

10

5

FDll GurDtion (FyFles)

(151)

10

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10

1

10

2

10

3

10

4

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5

FDll GurDtion (FyFles)

0

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(152)

µ

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(153)

0

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3

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8

TiPe spent in tFPDlloF (%)

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