ADC Super Net Technical Manual pdf

(1)

nCHNICAL MANUAL

for

SUPER NET

(2)

INTRODUCTION

. ADVANCED MICRO DIGITAL is proud to introduce the SUPER NET. The SUPER NET is a

za0

based single board computer designed

t" be a bus master in an 9109 bus system. The. SUPER NET SBC has all the hardware needed to run a single user CP/M system

or 2 user MP/M system with up to 4 external floppy disk drives and an external Centronics parallel interface printer all on one board.

The SUPER NET

sac

contains : 1) Z-89A cpu

2) Floppy disk c~ntroller (up to 4 drives

a

or 5 1/4 • ) 3) 64 k of dynamic memory ~16K bank selectible)

4) 2k or 4k of shado~ eprom (2716 or 2732)

5) 2 serial ports (Za9A 510 opt.syncronous)

6) 2 12 bit parallel ports, one of which can be used for 5100 vectored interrupts (Z80A PIO)

(3)

TABLE OF CONTENTS

~---~---Introduction _•_•_{• • • • • • • •}_•_•_•_•_•_•_{• • • • • •}_•_{• • • • • •}_•_•_•_{• • • •}_•_{• • • • • • • • • • • • • •} Table of Contents •••••••••••••••••••••••••••••••••••••••••••••• 2,3

2.0

Operation ••••••••••••••••••••••••••••••••••••••

1.1 Floppy disk ••••••••••••••••••••••••••••

1.2 64 K Dynamic Ram •••••••••••••••••••••••

1.3 Monitor Eprom ••••••••••••••••••••••••••

1.4 Serial Ports •••••••••••••••••••••••••••

1.5 Parallel Ports •••••••••••••••••••••••••

1.6 Real Time Clock ••••••••••••••••••••••••

1.7 5100 bus interface •••••••••••••••••••••

EPROM 2.1 2.2 2.3 2.4

and Mo n i to r •••••••••••••••••••••••••••••• Enable / Disable software ••••••••••••••• Monitor Sign-on •• · ••••••••••••••••••••••• Monitor Commands ••••••••••••••••••••••• Cold boot loader program •••••••••••••••

4 4 5 5

7 8

8 9

3.0 Input ~·Output port assignments ••••••••••••••••• 10

4.0 Input

/

Output port description • • • • • • • • • • ·1 • • • • • 11

4.1 SIO serial port channel A

.

. .

.

. .

.

.I. ...

4.2 SIO serial port channel B

.

. .

.

. . .

.

. .

.

11

4.3 PIO parallel port channel A

.

. .

.

. .

.

11

4 .• 4 PIO parallel port channel B

.

. .

.

. . .

.

. .

.

11

4'-.5 Control timer Interrupt circuit

· .

. .

. . .

11

4.6 Floppy Disk controller

. .

.

11

4.7 Floppy disk control port

.

. .

.

. .

.

. .

.

12

4.8 Extended address port

. . .

.

. . .

.

. .

13

4.9 On-board memo~y control port

. .

.

. .

.

14

5.0 Jumper definitions

.

. .

. . .

.

. . .

.

. .

.

. .

.

. .

.

. .

1~

6.0 Jumper descriptions

.

. .

.

. .

.

. .

. . .

. .

.

6.1 Jumper A CPU clock rate

.

. .

.

. . .

6.2 Jumper B

-

SIO channel A clock

.

. .

.

. .

6.3 Jumper C

-

SIO channel B clock

.

. .

6.4 Jumper 0

-

Drive type selection

...

6.5 Jumper E VIO / PINT

.

. .

.

. . .

.

. .

16

6.6 Jumper F

-

VIO / paralled bit 00

· .

.

. .

.

16

6.7 Jumper G

-

VII _/ paralled bit 01

· . . .

.

17

6.8 Jumper H

-

VI2

/

paralled bit 02

· ...

18

6.9 Jumper J

-

VI3 _/ paralled bit D3

· . .

. .

18

6.10 Jumper K

-

VI4 / paralled bit 04

· .

. .

.

. .

18 6.11 Jumper M

-

VIS _/ paralled bit 05

· . .

.

. .

(4)

1.0

6.13 6.14 6.15 6.16 -.6.11 Baud 1.1

Jumper P VI1 / paralied bit 01 ••••••• 19 Jumper·R 2116 / 2132 ••••••••••••••••• Jumper S Floppy connector •••••••••••• Jumper

T

Memory Write Signal ••••••••• 20 Jumper layout ••••••••••••••••••••••••••• AA Rate Switch •••••••••••••••••••••••••••••••

Switch Setting _•_•_•_{• • • • •}_•_{• • • • • • • •}_{• • •}_•_{• • • •} 21 21

8.9 External Connector pin definitions •••.•••••••••• 22

9.0 10.0

11.0

8.1 Jl S100 bus •• ~ •••••••••••••••••••••••

8.2 J2 Parallel Port •••••••••••••••••••••

8.3 J3 Floppy Disk controller . . . 2~

8.4 J4 Serial port channel A ••••••••••••• 25

8.5 J5 Serial port channel B •••••••••••••

Block Diagram •••••••••••••••••••••••••••••••••• Factory

10.1 10.2 10.3 10.4 10.5 10.6 10.1 10.8 10.9 10.9.1

Installed Jumpers· •••••••••••••••••••••• 8 inch drive configuration ••••.•.•••••••• 5.25 inch drive configuration •••••••••• Shugart 800 drive •••••••••••••••••••••• :shugart 850 ••••••••••••••••••••••••••••• MPI dr ive •••.••••••••••••••••••••••••••• MFE model 700 •••••••••••••••••••••••••••

MITSUBlsat model M2894 •••••••••••••••••• NEC 'model FDl160 . . . . QUME Data Track 8 ••••••••••••••••••••••• REMEX model RFD4000 ••••••••••••••••••••• Appendex & Data sheets ••••••••••••••••••••••••• 11.1 Appendex A Z80A 510 / DART •••••••••••

11:.2 Appendex B Z80A PIO ••••••••••••••••••

11.3 11.4 11.4.1

Appendex C Z80A CTC •••••••••••••••••• Appendex D Floppy Disk controller •••• WD 1691,BR1941 •••••••••.••••••••••••••••

25

26

27

28

29

(5)

1.1 The Floppy Disk Controller

-~--~---The floppy disk controller can access up to four 8 inch or 5.25 inch floppy disk drives. It can read and write IBM 3740 single

-density format, and double -density 128,256,512,1024 sector size formats. Data -transfer is done by programmed I/O with wait and

interrupt syncronization.

Note: The controller cannot access both 8 inch and 5.25 inch drives simu1tanious1y,The controller is switched from 8 inch to 5.25 inch drives by hardware jumper options.

1.2 The 64 k Dynamic ram

---~-

.

The 64 k ram array can be switched on and off in 16 k increments

(0-16K,16K-32K,32K-48K,48K-64K) under software control. This a1low~

t:

CPU to access bank switchab1e external memory on the 5100 bus.

The memory has an access time of 200ns. Refresh is done during Z80 M1 cycles and during wait and reset states. The memory can be accessed by an external DMA device on the 5100 bus.

Note : Any external DMA device that is using continous mode DMA cycles must transfer data at an average rate of 15 us per byte or

faster when holding the DMA request line for more than 1.5 ms This .s not a problem because most designers are smart enough to use

(6)

1.3 system Monitor Eprom

---~--~~---~

The sysiem monitor eprom is switched on during reset. It can be disabled"and enabied under software control. It resides when

enabled at F000h to FFFFh. I t bas commands that allow the user to load toe CP/M, MP/M'or other boot loaders from floppy disk.

J

In addition it can be used to load , exami~e goto and test

memory. When the prom is disabled i t does not use any system addres~

space.

1.4 Serial ports

A Z80A DART is used for the two serial ports , but

a Z80A SIO/0 chip can be used in i t ' s place. This allows

asyncronous and synchro~ous serial data communications plus a variety of interrupt modes. Modem control s1~nals are available at each

serial connector. There are- two switch selectible baud rate generators for baud rates of 50 to 19.2 k baud.

Note : The serial ports are TTL and must be connected to external interface boards ·for R5232 communications.

(PS NET/I)

(7)

1.6 Real Time Interrupt clock

A Z80A CTC is used for providing a real time system clock for MP/M. Three channels of the CTC are available to the user for strapping

a jumper header for synchronous baud rates or 10n9 c~ock times.

1.7 5100 Bus Interface

The 5100 bus interface provides the signals necessary for an 8 bit bus master as described by the IEEE 696 bus specification.

vectored interrupt lines VI0 - VI7 are supported via jumper options and A16 - A23 are also supported vis an I/O port.

(8)

2.0 EPROM and-Monitor operation

The onboard EPROM~ccupies address F000H-FFFFH. The EPROM

is switched on automatically during reset or power on, the

EPROM contains SIO and FOC initialization code along with a

simple debugger and floppy disk cold start loader. After

the operating system is loaded the EPRO~~can be turned off

so that the ram at address F000H-FFFFH can be accessed. The

EPROM can be turned on and off at any time so that hardware

dependent I/O routines can be called.

2.1 Eprom Enable / Disable

Switching EPROM on :

F033 3E4F .MVI A,0100l111B iRESET POWER ON JUMP

i AND ENABLE MEMORY, EPROM

F035 0316 OUT '168 iWRITE TO CONTROL PORT

Switching EPROM off

.

_.

.

F033 3E4F MVI A,0l101l11B iRESET POWER ON JUMP

; AND ENABLE MEMORY, EPROM

F035 D316 OUT 16H ;WRITE TO CONTROL PORT

Jumper R configures the board to accept a 2716 or 2732 EPROM.

Note : The EPROM is always addressed at F800H and can not

be moved. Since the 2716 EPROM is 2K long i t appears

ON

(9)

The monitor comm~nds are :

Control C

=

Load disk boot loader

D SSSS 0000

=

Dump memory in hex from SSSS to OQQO

F

ssss

OQOO SS = Fill memory from SSSS to OQQQ with SS

G AAAA = Go to address AAAA

L AAAA = Load memory starting at AAAA

M

=

Memory Test

P

ssss

QQQO

=

Print in ascii from SSSS to OQOO

R = Find system ram

S SSSS QQQQ

=

Search for byte pattern

T

=

Test Memory

ESC will terminate any command

The cold boot loader will select and home drive 0.

Track 0 sector 1 will be read into memory at location 0 • . -Single density is assumed for track 0.

If an errOL occures an error code will be printed. The error code must be translated using the table

in appendex F page F-4 fig 2.

2.4 Cold Boot program

F4BS 3E00 F4B7 OlSe F4B9 00 F4BA OB0C F4BC 0F F4BD OABAF4 F4C0 00 F4Cl 00 F4C2 00

; READ TRACK 0 SECTOR 1 INTO MEMORY BOOT:

MVI A,00H RESET FOC

OUT FOC ; ISSUE COMMAND

NOP FOCW1:

IN FOC ; CHECK BUSY

RRC

JC FDCWl

Nap KILL TIME

(10)

F4C3 00 NOP

F4C4 3E03 MVI A ,3 ; GET A RESTORE

F4C6 030C OUT FOC

· ,

ISSUE COMMAND

F4C8 00 NOP

F4C9 0814 IN WAIT

,

·

WAIT FOR

F4CB

""

NOP

· ,

INTRQ

TK0:

F4CC DB0C IN

Foe

F4CE E.604 ANI 4

.

,

CHECK TRACK 0

F4D0 CACCF4 JZ TK0

F4D3 AF XRA A

F4D4 6F MOV L,A POINT AT LOC 0

F4DS 67 MOV a,A

F406 3C INR A

F407 030E OUT FDCSEC ; SET SECTOR

F409 3E8C MVI A,08CH ; GET READ COMMAND

F4DB 030C OUT FOC ; ISSUE COMMAND

F4DD 00 NOP

FDCRD:

F4DE OB14 IN WAIT WAIT FOR INTRQ

F4E0 B7 ORA A ; OR ORQ

F4El F2EBF4 JP BOOTON EXIT IF INTRQ

F4E4 DBlaF

..

IN FOCDATA GET DATA

1:'4E6 77 MOV M,A STORE'

~ 4E'7 23 INX a POINT NEXT

F4E8 C30EF4 JMP FOCRD :

BOOTON:

F4EB DB0C IN FOC ; CHECK STATUS

F4ED B7 ORA A ; o = NO ERROR

F4EE CA0000 JZ

"

OK, GO

F4Fl FS PUSH PSW ; SAVE ERROR

F4F2 210FF6 LXI H,BTERR ; PRINT

F4F5 CDE6F0 CALL MSG DISK ERROR

F4F8· Pi POP PSW GET ERROR

(11)

3.0 INPUT I OUTPUT PORT ASSIGMENTS Address 00 01 02 03-04 05 06 07 08 09 0A 08 0C 00 0E 0F 10 11 12 13 14 15 16 17 18 19 lA is 1C 10 1E 1F Read/Write Read/Write Read/Write Read/Write Read/Write Write Read/Write Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write

,

Read/Write Write Write Function

SIO Channel A Data port

SIO Channel A Status/Control Port SIO Channel B Data port

510 Channel B Status/Control port PIO Channel A Data port

PIO Channel A Control Port PIO Channel B Data port PIO Channel B Control Port CTC Channel 0 Control port

CTC Channel 1 Control portol CTC Channel 2 Control port CTC Channel 3 Control Port FDC Command/States Port FDC TraCK Register

FDC Sector Register FDC Data Port

Unused Unused Unused Unused

FDC Syncronization/Drive/Density S101. Buss Extended Address A16-A24 On-Board Memory Control Port

Unused Unused Unused Unused Unused Unused Unused Unused Unused

All address are listed in Hexidecimal.

The unused input / output ports are internally decoded and

(12)

4.0 INPUT / OUTPUT PORT OISCRIPTIONS

Serial Communications Port A

---

See Appendex A

00 Read/Write SIO Channel A Data port

4.1

01 Read/Write SIO Channel A Status/Control

JIlt. Port·

~c. {. '.: I.,. ,_

4.2 Serial Communications port B

---

See Appendex A I",

t " / ,,; -.. ~

SIO Channel B Data port

02 03

Read/Write

Read/Write SIO Channel B Status/Control Port

4.3

4.4

Paralled Interface Port A

04

05

Read/Write Write

Parallel Interface Port B

See Appendix B

PIa Channel A Data port PIa Channel A Control Port

See Appendix B

This port can be jumpered via jumpers E through P to the

5100 vectored Interrupt lines or to connector J2 (see sec 6.0 )

06 07

ReaJ/Write Write

PIO Channel B Data port PIO Channel B Control Port

4.5 Control Timmer Interrupt circuit --- See Appendix C

4.6

08

09

0A 0B

Floppy 0C 00

0E

0F

Read/Write Read/Write Read/Write Read/Write

Disk' Controller Read/Write Re'ad/wr i te Read/Write Read/Write

CTC Channel 0 Control Port CTC Channell Control Port; CTC Channel 2 Control port CTC Channel 3 Control Port

See Appendix 0

FOC Command/States Port FOC Track Register

(13)

4.7 Floppy Disk Control port

14 Read/Write FDC syncronization/Drive/Density

Port Read :

When the cpu reads this port the cpu is placed into a wait state until a data byte can be transfered to or from the floppy disk controller or untill the command complete/terminate status

(INTRQ) is set by the floppy disk controller. The floppy disk controller INTRQ status bit is placed on the data bus as bit 07. This bit can be tested to determine if data is to be transfered of if the command is complete.

+----+----+----+----+----+----+----+----+

1 07 1 06 ! 05 ! 04 ! 03 ! 02 ! 01 ! DO !

+----+----+----+----+----+----+----+----+

!

1

+--

+---

+---~----

+---

+---~---

+---

+---Port Write :

07 = MSB, 00 = LSB

Don't care Don't care Don't care Don't care Don't care Don't care Don't care

INTRQ* 0=active, l=inactive

The low two bits 00 and 01 of this port control which drive is selected.

01 00

·0

o

1 1

o

1

o

1

(14)

Bit 03 sets the density mode. When bit 03 = 0,. single density is

selected. When bit 03 = 1, double density is selected.

+----+----+----+----+----+----+----+----+

1 07 1 06 1 OS 1 04 1 03 1 02 1 01 1 DO 1 07

=

MSB, 00 = LSB

+----+----+----+----+----+----+----+----+

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 +-- Disk drive select bit 00

1 1 1 1 1 1

+---

Disk drive select bit Dl

1 1 1 1

+---

Don't care

1 1 1 1

+---

Density, 0=single, 1=double 1 1 1

+---

Don't care

1 1

+---

Don't care

1

+---

Don't care

+---

Don't care

4.8 Extended address port

15 Write

See Section 8.1 (buss defination) 5100 Buss Extended Address A16-A23 port Write:

This port controls the 5100 Extended address lines.

+----+----+----+----+----+----+----+----+

1 07 ! 06 ! 05 ! 04 ! 03 1 02 ! 01 ~ 00 1 +----+----+----+----+----+----+---~+----+

!

1

!

'1 1 1

+--

+---

+---+---~---

+---

+---A16 A17 A18 A19 A20 A21

A22

A23

(15)

4.9 On-Board Memory Control port

16 Write On-Board Memory Control Port

This port controls the onboard memory managment circuit,

prom enable and disable and power on jump reset circuits.

port write:

The four low order bits 00,01,02 and D3 switch the on board memory

in 16k banks corresponding to address 0000h-3FFFh,4000H-7FFFH,

8000H-BFFFH and C000-FFFFH on and off. When a particular bank is

switched off, external S100 memory can be accessed in that

banks address range. This feature allows external memory to be

added to the system for multi-user operating systems.

Bit D5 of this port switches the on-board EPROM on and off. The onboard EPROM occupfes address F000H-FFFFH. The EPROM

is switched on automatically during ~eset or power on, the

EPROM contains SIO and FOC initialization code along with ~

simple debugger and floppy disk cold start loader. After

the operating sys~em is loaded the EPROM can be turned off

~

so that the ram at address F000H-FFFFH can be accessed.

Bit 06 reset the power on jump circuit. Bit 06 must be set

high after a reset or power on situation before ram can

be accessed.

+----+----~----+----+----~----+----+----+

! 07 ! 06 1 05 1 04 1 03 1 02 ! 01 ! DO ! +----+----+----~----+----~----+----+----+

! 1 1

1 1 1

+--

+---

+---1 +----~---

+---

+---07

=

MSB, 00 = LSB 1=bank on, 0=bank off Memory Bank 0000H-3FFFH Memory Bank 4000H-7FFFH Memory Bank 80Q0H-BFFFH Menory Bank C000H-FFFFH Don't care

(16)

Jumper Definitions

Jumper Function

~~~---

---A CPU clocK rate 2mhz/4mhz

B External/Enternal TX/Rx clock for 510 channel A

C External/Enternal TX/Rx clocK for 510 channel B

o

Eight inch - five inch Drive selection

E Select 5100 interrupt vector line VI0 OR PINT. F Select 5100 interrupt .vector VIO/PINT or parallel

Port B bit 00 on J2-2S.

G Select 5100 interrupt vector VIl or Parallel Port B bit Dl on J2-27.

H Select 5100 interrupt vector VI2 or Parallel Port B bit 02 on J2-29.

J Select 5100 interrupt vector VI3 or Parallel Port B bit 03 on J2-31.

K Select 5100 interrupt vector VI4 or Parallel Port B bit 04 on J2-33.

M Select S100 interrupt vector VIS or Parallel Port B bit 05 on J2-35.

N Select S100 interrupt vector VI6 or Parallel Port B bit 06 on J2-37.

P Select ~100 interrupt vector VI7 or Parallel Port B bit D7 on J2-39.

R Select 2716 or 2732 EPROM.

S Define floppy disk connector for eight ad five inch drives.

T E n a b l e / Disable 5100 bus memory write signal on J1 - 68

6.0 Jumper Descriptions

6.1 A CPU clock rate 2mhz/4mhz

(17)

Jumper B is located near JS.

+---+

1 1 1 _{·Connector JS pin 9}

+---+

1 2 1 SIO TX/Rx clock input +---+

1 3 1 _{Baud rate generator channel}_A

+---+

Install Plug between posts 1 & 2 for external SIO clock. Install Plug between posts 2 & 3 for Baud rate generator.

6.3 C External/internal TX/RX clock for SIO channel B

Jumper C connects the SIO channel B to either the internal baud rate generator or to connector J5 pin 9 for use in sycronous applications. Jumper C is located near J5.

+---+ _.'

1 1 1 Connector JS pin 9 +---+

1 2 1 SIO TxiRX clock input +---+

1 3 1 Baud rate generator channel B

+---+

Install Plug between posts 1 & 2 for external SIO clock. Install Plug between posts 2 & 3 for Baud rate generator.

6.4

o

Eight inch - five inch Drive selection

Jumper 0 is located near IC U2. +---+

1 6 1 8 inch floppy clock source +---+

1 5 1 FOC clock input +---+

1 4 1 5.25 inch floppy clock source +---+

1 3 1 5.25 head load/motor +---+

1 2 1 Head load source +---+

1 1 1 8 inch head load +---+

(18)

Note: There are 'other board modifications needed to interface

the

FOe

to a 5.25 inch drive.

6.5 E Select S100 interrupt vector line VI0 OR PINT.

Jumper E selects the interrupt line to be used when channel B

bit 00 is programmed for interrupts.

Jumper E is located below Ie'U8.

+---+---+---+

1 1 1 2 1 3 1

+---+---+---+

Install Plug between posts 1 &. 2 for VI0 interrupt pin. (Jl-4)

Install Plug between posts 2 &. 3 for PINT interrupt pin. (Jl-73)

6.6 F Select 5100 interrupt vector VIO/PINT or Parallel

Port B bit 00 on J2-25.

Th i s j umpe r i s loct~ ted 'nea r connec to r J 2. +---+---+---+

! 1 ! 2 ! 3 !

+---+---+---+

Install Plug between posts 1 &. 2 to connect the PIO bit 00:

to J2 pin 25 (when the PIO bit is programmed for input/output).

Install Plug between posts 2 &. 3 to connect the PIO bit 00

to the jumper sel~ctor area E, VI0/PINT (when thePIO bit is programmed for interrupt mode).

6.7 G Select 5100 interrupt vector VIl or Parallel

(19)

6.8 H

This jumper is

~elect Sl~~ interrupt vector

Port B bit 02 on J2-29. located near connector J2.

+---+---+---+

1 1 1 2 1 3 1

+---+---+---+

VI2 or Parallel

Install Plug between posts 1 & 2 to connect the PIO bit 02

to the vectored interrupt line VI2 (when the PIO bit is

programmed for interrupt mode).

6.9 J Select Sl~~ interrupt vector VI3 or Parallel

Port B bit 03 on J2-3l. This jumper is located near connector J2.

+---+---+---+

1 1 ! 2 1 3 ! +---+---+---+

Install Plug between posts 2 & 3 to connect the PIO bit 01-to the vec01-tored interrupt line VI3 (when the PIO bit is

6.10 K

This jumper

Select Sl~e interrupt vector VI4 or Parallel Port B bit 04 on J2-33.

is located near connector J2. +---+---+---+

1 1 1 2 1 3 ! +---+---+---+

to the vectored interrupt linr VI4 (when the PIO bit is

6.11 M Select 5100 interrupt vector VIS or parallel

(20)

This jumper is located near connector J2.

+---+---+---+

1 1 121 3 1

+---+---+---+

to J2 pin -25 (when the PIO bit is programmed for input/output).

Install Plug between posts 2 & 3 to connect the PIO bit 05 to the vectored interrupt line VIS (when the PIO bit is

6.12 N Select 5100 interrupt vector VI6 or Parallel

Port B bit 06 on J2-37. This jumper is located near connector J2.

+---+---+---+ ! 1 ! 2 ! 3 !

+---+---+---+

Install Plug between po~ts 1 & 2 to connect the PIO bit 06

to J2 pin 25 (when the PIO bit is pr~grammed for input/output).

Install Plug between posts? & 3 to connect the PIO bit 06 to the vectored interrupt line VI6 (when the PIO bit is

6.13 P Select 5100 interrupt vector VI7 or Parallel

Port B bit D7 on J2-39. This jumper is located near connector J2.

+---+---+---+ ! 1 1 2 ! 3 1

(21)

Jumper R configures the board to accept a 2716 or 2732 EPROM.

Jumper R is located near the Z80 chip. +---+

1 1 ! Address line All +---+

1 2. 1 EPROM input +---+

! 3 ! +5 volts

+-~-+

Install Plug between posts 1 & 2 for a 2732 EPROM. Install Plug between posts 2 & 3 for a 2716 EPROM.

Note

.

The EPROM is always addressed at F800H and can not be moved. Since the 2716 EPROM is 2K long it appears

twice

,

F800H-FC00H and FBFFH-FFFFH.

6.15

s

Define floppy disk connector for eight , five inch

drives and Foe chip type. This jumper is located U26.

+---+---+ ! 1 1 2 !

+---+---+

~ ! 3 ! 4 !

+---+---+

! 5 ! 6 !

+---+---+ 1 7 ! 8 !

+---+---+

Install Plug between posts 1 & 2 for 12 volt Foe chips (WD1793) Remove Plug between posts 1 & 2 for 5 volt only chips (MB8877)

Install Plug between posts 3 & 4 to connect HEAD 2 signal to pin 2 of J3.

Install Plug between posts 5 & 6 to connect above track 43 to pin 24 of J3.

(22)

6.16 T ~nable / Disable 5100 bus memory write signal on

J l , - 68

This jumper is located near U18.

+---+---+

1 1 1 2 1

+---+---+

Install Plug between posts 1 & 2 to connect the memory write signal (MEMWR) to the 5100 bus pin 68.

7.0 Baud Rate Switch

The baud rate of the two serial channels can be select separately

by setting the baud rate switch. The baud rate switch is an 8

pole switch located near U54. It is split into two sections.

Switches 1,2,3,4 set the baud rate for the SIO channel B and

_.

switches 5,6,7,8 set the baud rate for the 510 channel A.

+---+

OFF (up)

SW1 ! 8 ! 7 ! ~ ! 5 ! 4 ! 3 ! 2 ! 1 !

+---+

ON (down) (- Channel A

->

(-

Channel

a

->

7.1 Baud rate switch setting

Switch 8 7 6 5 ChannelJW baud rate

(23)

:~:::~---~---~---~---:---:~:~~::~-~:~~-::::---off on off off 7200

on off off off 9600

off off off off 19,200

For exact baud rate frequencies see Appendix 0

8.0 _{External Connector Pin definitions}

---~---8.1 Connector Jl _{5100 bus connector}

insert page 28 & _{29 from IEEE - 696 specification}

8.2 Connector J2 Parallel port connector

1 ARDY _{PIO Channel A ready signal}

2 AROY RET ground

3 ASTRB· _{PIO Channel A strobe}

4 ASTRB RET ground

5 PA0 _{PIO Channel A data bit 00}

6 PA0 RET ground

7 PAl _{PIO Channel A data bit 01}

8 PAl RET ground

10 PA2 RET ground

..

12 PA3'RET ground

14 PA4 RET ground

15 PAS _{PIO Channel A data bit 05}

16 PA5 RET ground

18 PA6 RET ground

20 PA7 RET ground

21 BROY PIO Channel B ready signal

22 BRDY RET ground

23 BSTRB· _{PIO Channel B strobe}

24 BSTRB RET ground

•

2S PBS _{PIO Channel B data bit 00}

26 PB0 RET ground

•

27 PBl _{PIO Channel B data bit 01}

28 PBl RET ground

•

29 PB2 _{PIO Channel B data bit 02}

30 PB2 RET ground

•

32 PB3 RET ground

•

34 PB4 RET ground

•

35 PBS _{PIO Channel B data bit 05}

36 PBS RET ground

(24)

*

38

39

40

PS6 RET

PB7

+ 5 VOLTS

ground

PIa Channel B data bit 07

* Note : These pins can can be jumpered to the S100 bus

8.3

vectored interrupt lines.

Connector J3 _{Floppy disk connector}

8 inch 5.25 inch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7--8 9 10 11 12 ground

Alternate Head 2* , ground

N/C ground N/C ground N/C ground N/C ground N/C ground Head 2* grouE:ld N/C ground Head load* ground Index* ground Ready*. ground

Above Track 43* ground

Drive select 0* ground

(25)

43 44 45 46 47 48 49 50

8.4 Connector

1 2 3 4 5 6 7 8 9 10 11 12 13 14

8 .5 Connector

1 2 3 4 5 6 7 8 9 10 11 12 13 14 27· 28 29 30 31 32 33 34 J4 N/C DCDA* SYNCA* RxDA CTSA* TxDA RTSA* DTRA* TX/RxCA* GND N/C

+16 VOLTS -16 VOLTS

+r VOLTS

J5 N/C DCDA* SYNCA* RxDA CTSA* TxDA RTSA* DTRA* Tx/RxCA* GND N/C

+16 VOLTS -16 VOLTS +S VOLTS

ground

Write protect* ground

Read data* ground Motor on*

ground N/C

Serial port Channel A

Data Carrer Detect Channel A * Sync Detect

Receive data Clear to send Transmit data Request to send

Data terminal ready

Transmitt / receive clock

Serial port Channel B

Data Carrer Detect Channel A * Sync Detect

Receive data Clear to send Transmit data Request to send

Data terminal ready

(26)

+---+

I connector I +-+---+---+

1 1

+---+

I +---+jumpersl

1 I +--+----+

+-+---+--+ 1 · ·

1 parall~l 1 1

1 ports 1 I

+--+---+ 1

1 1

+---+

1 connector 1 +---+---+

1

1 1

+---+---+

1 Floppy diskl

1 controllerl +---+---+

1

+----+ +----+

lconnl lconnl

+-+--+ +--+-+

1 1

1 I

+-+---+-+ 1 A Serial B I

I ports 1

+---+---+ I

I +----+---+---+

1 1 +-+ I I

I 1 1 I 1

+---+ 1 1 +---+ +---+---+ +---+---+

! clock! 1 1 1 eproml I CPU I I Ram Array 1

I 11 I 12k,4k+--+--+ 1 1 1

+---+ 1 +---+ I +---+ +---+---+

I I 1

1 I 1

+~---+--+ +---+---+ 1

1 data rec.1 1 S100 address 1 1

1 /drivers 1 1 drivers _, 1

+---+ +---+---+

1 !

--!V! +---+

!lines 'I

+----+---+---+---~:--+

5100 BUS

(27)

10.0

10.1

Factory Installed Jumpers

Factory Installed jumpers for 8 inch floppy option

Jumper

A

B C

o E F G

H J

K M N

P

R

S T

2-3 2-3 2-3 1-2,5-6

1-2 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-1 5-6,7-8 1-2

CPU clock. 4mhz

TX/Rx clock. for SIO A .internal TX/Rx clock for SIO B internal Eight inch Drive selection Select vector line VI0

Parallel Port B bit 00 on J2-25. Parallel Port B bit 01 on J2-27. parallel Port B bit 02 on J2-29. Parallel Port B bit 03 on J2-31. parallel Port B bit D4 on J2-33. Parallel Port B bit D5 on J2-35. Parallel Port B bit D6 on J2-37. Parallel Port B bit D7 on J2-39. Select 2716

Define floppy disk connector

(28)

10.2 Factory Installed jumpers for 5.25 inch floppy option

Jumper

A B - C

o

E F

G

H J K M N P R

S T

2-3 2-3 2-3 1-2,5-6 1-2 2-3 - 2-3 2-3 2-3 2-3 ' 0

2-3 2-3 2-3 2-1 5-6,7-8 1-2

CPU clock 4mhz

Tx/RX clock for S10 A internal Tx/Rx clock for S10 8 internal Eight inch Drive selection Select vector line VI0 Parallel Port B bit 000

on J2-25. Parallel Port 8 bit 01 on J2-27. Parallel Port B bit 02 on J2-29. Parallel Port B bit 03 on J2-31. Parallel Port B bit 04 on J2-33. Parallel Port B bit 05 on J2-35. Parallel Port B bit D6 on J2-37. Parallel Port B bit D7 on J2-39. Select 2716

De "ine floppy disk connector

Enable S100 bus memory write signal Resistor R4.is changed to 220k oohm

(29)

10.3 Shugart SA 800 Jumpers

Disk drive jumpers

Remove al~ jumpers on the disk drive. Install jumpers as follows:

Jumper

Y-Jumper 0

Jumper T3 ,T4 ,TS ,T6 ~.

Jumper Tl-Jumper 800 ...

Jumper X

Jumper A .

Jumper B

Jumper OS "

(30)

OS2"-10.4 Shugart 850

Disk drive Jumpers

Jumper 28

Jumper D

Jumper A Jumper B ... ;. Jumper R Jumper I· Jumper Z

Jumper 850

(31)

10.8 ';EC tOouel FOl160

Dizk driv Jumpe.3

Install jumpers as follows: Jumper C

Jumper N

Jumper HLS

Jump"er _ M

Jumper PRt

Jumper OLD

(32)

10.9 QUME data track 8 Disk drive jumpers Install jumpers as follows:

OS1 OR OS2

o

C (OPTIONAL) OC

(33)

(34)

o

c

B

,.

L

....

-.- J ___ .-.

-1·----·· ---

-,..----.---UH

L")Oi

L2[>b

U34

L~()4

(le ~)_-4-_--"J---,I.:..1 Co

,

c

(8j

__

.I'"> •• r UI3

~ L'iOO 1

(H1)

-~~e+-

__

~p~D~B~IN~

____ - .

,.----~ 1

+-_P'--').;:..T...;V:....A....;:L'-(14-<.~tl~

~

~ ~ \.B i:Jf-'q4---+----..., <;ut'Z.. S L "l00 r.1....""&4--,-P-,-,Wc"R,--(4-B1)

l~?4 10) L'??2

11 I( _~---(I-Ot.)- - - - WR

~

11 'jII-JP

~ L5 \6 k)----=~---;--<. ~ -B 7)

_ 1...-4-_ ... ':=-L.._/ I l.." _

MI 3 51f,JTA

(I.Ob)'-:....:....--... ~ 1)41 Z L')QO t)::.-4---"---ll·B7J

_ _ _ 4'-jl L-10 ~()f>_-+-_ _ _ -,-,)()=UT1HI7)

.,1 j

r- '-I

; u,q. 1-'11..:....,.. _ _ _ _ --.

~.t\ I---O<c I T '

j

i'-_~

74~e 11 7 " ' - - - • oc

POC . 9." - - - ' ; t-. P l~/'~~) CLOCK 4'3 9 UIS lI.!/o,,---+-__ 2.:...!MJtt(~'~1)

~ 24 1--"::70:~~--""1'" 5t90 ~ ~~'l.u~

M wRITE. ct-B

1_-4---:-<.)':-_

~ ~2=---~8~ L5~ a (~ 2. ~~ SL

RM~

.

.r~'" y.'V\, ~- • . ,

'5D5e lOI--_'T.,.fl_I-=:.j) u.a Ii?

...-_ _ ....;S;;..IN.;..P_ (2-C~) " . . . ,

: L5O-4

~Mi 11~---~~~

t;IWP 4{,1---~.~

':,.\.ILT A .,a I - - - . ! . J I A~

';)II-JT A % 1--_ _ _ _ _ _ _ _ _ ,7

I,!, ISA

II

! v v v

.J.. 47 pf

~

U4Z,

Ll .. _ •. i I. ... ftC

-.- L-____________

--.l:..~.Q..."~_

RI\& 10

RA5 1\

~ _It.

RAJ I!.

RAl I~

RAI .:1 RAO I ..

l'

RMB

eARI-I>AI~

(104)(1-C.<\)

eA0 '1

Bill 11

BAt 4 8A3l!i BM 6

BA') \}

Mb 8

BAl II

SA6 t

BA~ 1 J!.AI~ 4

.fAil I~

,Qm Jj

eAt} I' SAUl! BAI~1J Ubb 2~

L

U&8 L'jZ40 L~240

I~ IlA0 , P.At 10 RJ.Z ~ liB

II,. fU~

17 RAt;

,Z R1C.

9 RA1

1& ~AG

I~ RAI

1'- RA1

I~ ~A3

4 Ii1M

h ItdS

112 RA.Ce>

9 RAl

rI I -

rI I t

I I

-

Ub4-11

,I

UE>~ t - - UE.2

t

I I

r

-

rt

-~

I "

-19 " U4& 9

1

... _ ... _ _ _ _ _ +-+-_ _ _ _ _ _ _ _ _ +-..=8_qL'::.132. f

'----...._-JT-1-"'1(\.:..-_ ....

I I I I I l "

t

r

t t

r

-,I

U61 ~ UtlO

(35)

o

c

8

A

I

L

__ 8 _________ ~ ________ ~1, ________ ~ __________ 6__________ . _ 5 4 3

---_.---_.---l'·'.'· .

V-3-~2.-Lt__=---

JS

__ ... _____ .. ________ . _. _____ .. . . _ mf"T . ________________ ---_._

_._---_. -_._--_.

__

. - - - . - - - -.. ---~~.--- - - - ----.

_.

--....----_.-

_._---_

..

_---."

~

r---"1

r-- ,~ ~~- u

I + 1 1 - 12

U5l.

~I

- 1 & - "

1-"':...:---1 2

~II"'---t }

t-", ... t - - - I 4

""',.,0 _ _ _ _ _ --1 ')

rl~')---I (Q

~I..:..l---I 1 r'~b~ ____ --I 8

~

u

n

-

~06---_f~

40-- ' - -to

,1i

r ' 1 - ' - - - t - - - - t 6

J-!'i..::.z _ _ --t _ _ - f 1

\-c"'1..;..'l _ _ --t _ _ - f ,

!-=1=-6 _ _ - t _ _ ~ 4

~l.!..~ - - - - t - - - f ~

j!o ~

24:-,,-_ _ t--_ _ i 1

W, " ~

~-5-14 ~1'1- tz

- I b - B

10

'

-BtoU 0 A

(.3' DB' :\iT

. I' ~DI

BlJ2

e'04

BOC,

De "

~.--~

02 I

O~ 'D

04 .,.,

0'; ~"

00 ~

0 7 1

r 4 -o~) (-,-,-A I'--_ _ --"~;

2 UII

I 9 Ie

"

14 ,~ 16 41 SWI

\~~J'6

9 e 7 6i

~

4

.~

_J

yz. XUL ?O"BOMl-tZ

I

101(

U9

8

Il.. _,

<t

2

r"

J2

r--+ , ) - 4 0

rl;;::;a _ _ _ _ _ ~ 1 ARO'!'

r~-"'---__I3 A'; T RE'J j-"-:-'---t., PA~

r'li.:..-_ _ _ _ _ -Il PA 1

I) ." PAl

11 1\ PA'

10 I!I PM

~ I~ PA"

It) 17 PACD

1 _ _ _ _ _ -I~ PAl

- - - t 1 1 6..B.QL..

11 13 B,)T Re>

- '7 - 2 ~-1 ~~ ~e. ~IO ~12 ~14 ~\-b ~IO ~70 ~22 ~l4 ~2~ ~la ~;O ~}1

00 1'1

0\

02 11

D4

0-;

D1

'}IP-'

---2' '>

10 1

RIO

I.',,\(

.~~!

l

!t~

1 u.

",f

1 ~.~

~ non.

J

~

~O~ 0-1 ')04

--- ---,: .. non..

1\7

L~~4

8Mlh YI tH1}.:..:.P,;::,OC=---vj---I

~

Ulb

UI L.,07 l';ln

01 Ie 01

tJ 1'2. I ...IT'

t5~~P;

C.

211'. 4.'1tl\7

B.iiin'W CJ -BZ.)

In

1 __ -:~::7-_ _ _ _ _ ..w17,O UI1

O"l 14 0

01 '7 0

01 :3 0

O~ 4- 0

:

.,.1-8(.

8AI4-\,I-C. ~)

I

J 1

.:~)

' - - - -... , '].1'1

9

PART O<l H04'(o,cU.rUR(

r-~~~---~--I~~~~-Tl~~I~~C-~~-~---~PA~R~r~sO<l~l~I~~T~~R-'P-'~~---~---~~

U"USS orw(IhoIS( SM:CIF'(O

OI"("S~S Alit I~ 1h(;,,(S TOI.ER'-"'ClS ARC

rIlACT~S O(CIMALS AIfClU

lJl := :; 110 "

SUPER< NET 5-100 BOARD

ADVAOC((D MICRO DIGITAL CORP.

SC4E MATIC

o

c

B

(36)

o

c

B

I

1

8 6 5

C.6

r;;·fl

.~

R4

'til I~ 33K

0

.- Q

•

It M\.Il(~'b'){H'\

0

l5\'n _r-<>5

1 ~~l

U4

~

40 _So MOTORO~·

Cll? 1'---1 Z

3Y I

·5

U2

I,.

, _{LSI ..}

Ct'&b) 00·01 ~B

liLT 1<- 6 5

~'~

H

uu. !.~

%

~ 1 21

01 a 1'3

01 q 'i'l

~ 10 ~e

.0; _0'1

"

1(.0

UIS ()5 II rC'I 1';

l504 RI6 _D(;' _n 0" _,.... _~o

... 2 , UI4 lot DI 14

>

L

,

_....,

.l I

0-1ne c:

2 RlI ₀

"

I

uzo

~

HJlRQ lOt ₊₅ _~ "l UI'3 ~ l

l'I'O~l I ₁ ₃₉ 1\ l. ~ WD

~~")~( ~I 1 4 ") ~14~

(I.e,) rDC WII.I1 DRO ~e

,.

I' ~

"

b l~~Z 2

'!> UZ2. _(\e~l _5!' .. 'e \~ Oi _17~'8

UZ£ R2.0 ₁ H ! \0

"

(I·e'l) ~ lOr.;> (I,e~) W>I Q

A~ ~ a IZ 10 • JO: 1 '220 .. 11

I~oa;{ '" _to ₎₁ I"; ;: , -J...~:'3 .L:,Ioj;.17 L'L

IJ

FOCC5 .')

..

Ij& ~ ,,,~.1.f

(I,C1\

!s _~ =:= ,I,J "

n .. I

,,!

,I"~

'r

('·B7)(.HE) ~ \7

o-!Q _~

~[

.12 --<>

OR. NC

.. 0; R2.1 ₊₅

(2. RI

1

'l'20A..l14 ·VI= :0 K.

lOO.uF ;'JO~

.

r:

1:

LI

:l

MOTORO~" .12.

121

0

IS b

U4

,

1

r

C.2~

LTU ~ . .'

l'j12' un em .l.,f (I.S",)

9p

l~Ol RZ-' _~ _{.!;} ...}

p-·a~ c. 2.1 \01.

\ L';I24

RU )

• IIl5

.I.t' • 41K .,

(z-n'l.z'C t) P .... R 1<lLJ (LA

~~A D0 ~

1\ UI

.

UIO

IL 01 ~ 'Z

LSn5

02 II.

,

T

, O} \;

"

-c. \01

1\ C

("fJl)~ 't

I

lJ~

1 •

1 L'?Pfl

I

,'~

3

RM~

+~

,

220/">".10

vr

:5 ~ 7

~Q (lR 3

l51n

'U.3

~

u

I

'~l

A & I

+~

1~ R3 2.~p( 10/\

~ u~z 9 ~

\1 110 1 _"

.!l _..,

v-

0 _~

_1:5 1400 12

(

Ii'

•

~

--llc CLl? Q

J

is

U3

L~~'

_Cll<

(,~ 71

CI~15

4 _...5

~ I

b ..,}

1 .~

.01 .... £ 10K

b<:~) PCW(R "AIL UI B

?

1401 14

-{>-

6

eo

t5

LSl4 Z ~ .IT [I

ut

0

::r---UI4

:B·b

-,n

r

-22 20 ~'l H 46 1 104 t" Ie. H '>8 - - ~ i

..---'" :z ii Q Q 0

i

.-

4~ I 'V 40 2" '10 }O }'2 2 REAO'i HlO€.X TM'KQ R[VISIOftS

WRIlE. PRClTt.CT

READ OATA

~EAO 2fTKH

TKH

~

~E 00 LOA.O

DIR":

WRlre. OAtA

SHP

1

o

c

(37)

7

• s

+

4

Pl

(38)

5

7

,

/I

IJ

IS /7

,"

.lS'

27

.1"

.31

33

3·7

PA

t:#

13'

~-z.

i>-

-81-~

....a-

-d(l-

--61<l-

--D'-~

i31Jt/

(301

Bo~

S 0.3

GOS"

7

f'

Attf

P

i~IOf:i1

#'

$7- IICJ3'O

~

,

.,

8 t:l

II

I~

3"Z..

I"

~I

(39)

Dear Cus toner ,

This is the board layout of SUPER NET with j~ areas.

Be sure to notice that Pin 1 of the header connector on the

top of the board is on the left, do no~ plug disk and I/O

cable in backward.

r1AY CAUSE DN1AGES.

Thank you,

(40)

I. '1

~

('., 1 '. I

- r, J

t

i o j ....

-" II

(41)

Pin •

1

2 1

"

5 6 7 a 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Name

+3 VOLTS +16 VOLTS

XRI7t

VI"

_VII

vn

VI1 VI~ VI~

VI?

~I

E=WRt"IL

!:MAl

Ala Al6 A17 StSe (li;B CND NDEF ArES [)JC68 b pSI'VAL pHDLA RFU RFU ~ ~4 ~3 A1S ~12 A9 OOllDATAl

00 O/CATA 0 ~10

004;t;ATh4

OOS/DATl\S

oc

p:> . .

r.

rx:

PlW'er.

Ceacrlptlon

01. of t"-O ready InPJt8 to the current b~ master. "th.

bl8 1s ready ~en both these ready slgnals are trUi.

See pin 72.

Vectored interrupt llne·O. - Vectored interr\¢ lin. 1. Vectored interrupt line

2.

Vectored interrupt line

.3.

Vectored interrupt line 4.

Vectored interrupt line

S.

Vectored interrupt line 6 •.. Vectored Interrupt line

1.

Non-maskable interrupt.

Po~r fall bt.8 Signal.

Temp:>rary master pclority bit 3 •. Extended address bit 18.

Extended address bit 16. Extended address bit 17.

The control signal to disable the 8 status signals. The control signal to disable the S control output

signals. .

Common wi th pili 100.

Not to

t::e

defined. Manufacturer-speci fied 1 ina.

The control signal to di.5able· the 16 address signals. '11ie control signal.to disable the 8 data output signals.

'11ie master timing signal for the bus. .

Status valid strobe.

A cont rol signal used in conj unct ion wi th HOLJ5 to coordinate bus master transfer operations.

Reserved for future use. Reserved for future use. Address· bit S.

Mdres5 bit 4. Address bit 3. hjdress bit 15. Address bit 12. .address bit 9.

Data out bit 1, bid! ractlonal bit 1. Data out bit 0, bidirectional bit O. Address bit 10.

Data out bit 4, bidirectional bit 4.

(42)

•

Name

....

-

...

---to 006jt)1\TA6

41 O[2/DATA1O

42 O[ 3/CATAll 43 O[7IDATA1S

~4 sMl

45 sour

46 sINP

47 sMEMR

48 sHTtA 49 CLOCK

50 '3NO

51 +8 VOL.TS 52 -16 VOLTS S3 GND

54 StAVE CtR

55 S~O

-~

~') :MAl

57 :MA2

sa

sXTRQ

:: j _A19

.:. ,

_.3:

_:(~

)

. ~20

.~ 2 _~21

.;; 3 A22

~~ _{. -\23}

.,5

~mEF

Description

---~~---Data out bit 6, bidirectional bit ~.

oata

in bit 2, bidirectional bit 10.

Data in bit

J,

bidirectional bit 11.

Data in bit

1,

bidirectional bit 15.

The status siqnal Which indicates that the current

cycle is an opcode fetch. "

The status siqnal identifyinq the data transfer bus

cycle to an output device. "

The status signal identifying the data transfer bus

cycle fran an input device.; " ..

The status signal identifying bus cycles Which transfer

data fran memory to a bus master, which are not

inter-rupt acknowledqe instruction fetch eyelets) •

The status Signal which acknowledges that

a

HLT

instruction has been. executed.

2 ~Hz clock. Not required to be synchronous witll any

other bus signal.

Common with pin 100.

Common with pin 1.

CC t:Ower.

Common with pin 100.

A reset signal to reset bus slaves. Must be active

wi ':h ~ and may al so'be generated by external means.

Temporary master priority bit O. Temporary master priority bit 1.

Tem~rary master priority bit: 2;

The status signal Which requests l6-bit slaves to

assert S!

XTN •

Ex tended address bit 19.

7he si~nal generated by 15-bit slaves in response to

the l~-bit request signal sXTRO •

Extended address bit 20. Extended address bit 21 • Extended address bit 22 •

Ex tended address bit 23 •

(43)

Pin , 70 71 72 73 74 75 76 77 78 79 3C 31 82 83 34 qc, ~ I '18 8) 90 91 92 93 '~4 93 97 99 99 100

Name Description

---

~~--- .~---~---~D RFU ROY RESET pS'xNCH

?'ffi

pOOrN AO A1 A2

. l\6

A7 A8 A13 ~.14 All 002/0ATA2 003/rATA3 007/DATA7 D14/CATA12 D15/DATA13 D16/DATA14 D1l/CATA9 D10/DATA8 sINTA ffiROR FOC GND

Common with pin 100. Reserved for future use.

O'le of two ready inp.1ts to the current bus master. The bus is reooy ....nen both these ready signal s are tr ue.

See pin 3.

The pc imary interrupt request bus signal.

The control signal used in conj lJ'lction wi th pHDl.A to bus master transfer operations.

The reset signal to reset bus master devices. This sig-nal must be active with

POe

and may also be generated by

external means.

The control signal identi fying BSl.

The control signal identifying the presence of valid data on DO bLS or data bus.

The control signal that requests data on the 01 bus or data bus fran the currently addressed slave.

Address bit 0 (least significant) • Address bit 1.

Address bi c. 2. Address b~ t 6 • Address bit I .

Address bi t 8.

Address bit 13. Address b~ t 14. Address bit 11.

Data out bit 2, bidirectional bit 2.

Data out bit 3, bidirectional bit 3. Data out bit 7, bidirectional bit 7. Data in bit 4, bidirectional bit 12. Data in bit 5, bidir~ctional bit 13. Data in bit ~, bidirectional bit 14. Data in bit 1, bidirectional bit 9.

Data in bit 0 (least significant bit for a-bit data) , bidirectional bit 8.

The status signal identifying the bus input cycle(s) that may follow an accepted interrupt request presented on INT.

The status signal identifying a bus cycle Which transfers data from a bus master to a slave.

The bus signal signifying and error condition during present bus cycle.