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Delay Test for Diagnosis of Power Switches

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Figure

Fig. 1.DFT for testing power-switches [5]. (a) Fine-grain design. (b) Coarse-grain design.
Fig. 2.HSPICE simulation to determine optimal segment size.
Fig. 4.Hardware implementation of control logic of a design with “m”power switch segments.
Fig. 6.Simulation setup to analyze the effect of process variation on thediagnosis accuracy of the proposed algorithm.
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