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On-chip hybrid superconducting-semiconducting quantum circuit

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Figure

Fig. 1: The schematic view of the Inheterostructure. The In  0.75Ga0.25As/In0.75Al0.25As/GaAs GaAs quantum well 2DEG with 30 nm thickness
Figure 2(a) shows the schematic view of the on-chip hybrid superconductor-semiconductor circuit consisting of eight symmetric and planar Nb-InGaAs-Nb Josephson
Fig. 2b. At the last stage, 10/50 nm thick Ti/Au layers was evaporated on top of the junctions for electrical measurement purposes
Fig. 5: Temperature and magnetic field B dependence of induced superconductivity. Red circles are dV/dI at temperatures between T= 300 mK  and 1.5 K

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