I
I I
THE DEVELOPMENT
OF INTERACTIVE FACILITIES
FOR THE
DDP-516 DIGITAL COMPUTER
by
Andrew John QUAINE
Thesis submitted for the
Degree of Master of Science Australian National University
June 1972
. l
l l
STATEMENT OF AUTHORSHIP
Unless otherwise specified by reference or
acknowledgement, the work presented in this thesis
is entirely my own.
. . .
l l lACKNOWLEVGEMENT
Software development for a computer system is always dependent on
software which has already been implemented. I acknowledge therefore the assistance
provided by the programming and system
support software supplied by Honeywell Inc. In particular, an unpublished paper by
J.W. Grondstra on the programming of the multiline controller was of assistance the design of the character driver.
.
in
I should like to record my
gratitude to my supervisor Dr D.E. Lawrence, of the Computer Centre, ANU, for his
guidance and encouragement throughout the project. I am indebted to Dr. G.W. Gerrity, of the Royal Military College, for
ABSTRACT
The development of basic system support
routines for interactive computing on a 32 Kbyte
DDP-516 digital computer is described. The system
lV
envisages up to eight keyboard terminals using 110 baud
asynchronous transmission in full duplex configuration. The minimum hardware interface provides one bit capacity per line. Input serial bit strings are sampled at four times the bit rate . Character serial/parallel
con-versions are software driven under fixed rate interrupt
control, requiring 6% of available machine time.
Backing store is provided by two moving head
disc storage drives using removable packs of 6 Mbytes capacity. The record size is 99 words, including
three words used for record and file control. Format procedures for optimum track packing have been devised, together with an interrupt controlled driver for disc
input/output using multiplexed acLe ss to core storage. The data transfer rate achieved is 128 Kbyte/sec, giving
a core-disc swap time of 500 msec for a 16 Kbyte execution module. The roll-out operation includes a
V
A time-sharing monitor for multi-user scheduling and control is proposed. The design is based on two
memory partitions assigned to users, one of which is in
execution while the other is either dormant or core-disc swapping. The monitor is core resident in a third
partition and protected from the current user.
Inter-communication between user modules and resident monitor
routines traps via privileged instruction execution.
Resident routines and drivers are either terminal
particular for parallel processing, or reentrant for
multi-programming usage.
A general purpose file processing package,
including line and character editing facilities, is
provided for use from remote keyboards . The command format for control of this package, as _well as that for overall system control, has been selected to avail the
novice or casual user of maximum system assistance,
while optionally providing the capability for fast
interaction required by the more experienced . The modular design of the interactive s ystem ensures its ready adaptability for expansion or interfacing of
packaged software. Extensions t o the basic system are
foreshadowed, and options for the improvement of system
vi
TABLE OF CONTENTS
PAGE
ACKNOWLEDGEMENTS
e • G • • • • • • "..
.
...
..
.
• 0 • l l l
ABSTRACT
0 • • • 0 • • • 0 0 0 e 0 0 0 • • • 0 • •"
.
.
lV§ 1.
INTRODUCTION
Machine Hardware • 0 • 0 0 0 • 0 •
.
.
.
lolInstructions
.
.
.
• 0 • 0 0 0 "..
.
.
.
1.2 Conventions.
.
.
• 0 • 0 • •.
.
.
.
.
.
1.3 System Objectives 0 • • 0 • •.
.
.
.
.
.
1.4 § 2 .CHARACTER INPUT
-
OUTPUT
Introduction
.
.
.
0 0 O • • 0.
.
. .
.
.
2.1Multiline Controller • 0 •
. .
.
.
.
.
2.1 Driver Routine.
.
.
0 0 0...
.
.
.
0 0 0 2 . 2 Routine Scheduling • • • 0 • • 0 0 0.
.
.
2.4 Processing Tables 0 0 0.
.
.
• 0 •.
.
.
2. 6Character Input 0 0 0 0 0 0
. .
.
0 • • 2 . 8Extract Routine 0 0 O 0 • • • 0 • • 0 • 2.10 Construct Routine 0 0 O
...
0 • •.
.
.
2.14 Output Routines • 0 • • • 0.
. .
0 • • 2.17 Seriialize Routine • • 0 • 0 • • • • • 0 • 2.17 Character Output • 0 •.
.
.
0 • • • 0 • 2.21 Echo Routine 0 O 0 • • 0 • • 0 • • 0 • • 0 2.21 Driver Timing 0 0 0 0 0 0 • • 0 0 0 0.
. .
2.25Driver Listing 0 0 e 0 • • • 0 •
.
.
.
.
.
.
2.30 § 3 0LINE BUFFER
CONTROL
Introduction O O 0 • • • 0 0 0 0 • •
.
.
.
3.1 Terminal Units 0 • • 0 • •. .
...
.
.
0 • • 3.1 Buffer Modes.
.
.
0 • • • 0 • 0 • •.
.
.
3. 2 Driver Independence 0 0 0..
" • • • O O 0 3•
TABLE OF CONTENTS (eontinued)
§ 4 .
FORTRAN
INTERFACE
Introduction 0 0 0
.
.
.
• 0 • Memory Lockout Option.
.
.
Compiler Generated LinkagesLinkage for Terminal I/0 . . .
Monitor Response o••
Terminal I/0 Functions
Interface Listing
§5.
VISC
FORMAT
Introduction
Disc:! Hardware
Track Format
Record Address
Records/Track
Record Format
0 • •
.
. .
• 0 • 0 0 0
.
.
.
0 0 0
.
.
".
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
.
Read After Write CheckInterrecord Gap
File Format
Disc Allocation
.
.
.
§6.
VISC
INPUT-OUTPUT
VRIVER
Introduction O O 00 0 0 0 0 0
0 0 0 Record Transfer Routine
Record Sequences
Request Selection
Table Search .•.
.
.
.
• • •
0 0 0 Driver Initialization
.
.
.
. .
.
0 0 0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
• 0 •
.
.
.
• 0 •
.
.
.
• 0 •
.
.
.
.
.
.
...
"• • •
Immediate Response Routines
Delayed Response Routines
Driver Timing
Driver Listing
• 0 •
. .
.
§7.SOURCE
FILE PROCESSOR
Introduction • • 0
• 0 • 0 O 0
• 0 • File Format and Buffering
Options • • 0 0 .. • Director Decoding file Editing ..•
Memory Size
Buffer Indexing
.
.
.
.
...
.
.
.
• • 0
.
.
.
• • •. . .
....
.
. .
.
. .
.
.
.
.
...
...
• • •• .. 0 0 • • • • 0 0 • • • • 0 0 • •
0 • •
.
.
.
.
...
0 • •.
.
.
.. ...
• 0 •
• • •
.
.
.
.
.
.
• • •
.
.
.
0 • •
.
.
.
.
.
.
.
...
• • •.
. .
.
.
.
• • 0
.
.
.
• • •
.
.
.
. .
.
...
.
0 • • • • 0
.
.
.
0 • •
.
.
.
.
. .
• • 0
.
.
.
.
.
.
.
..
.
. .
0 0 0
.
.
.
• 0 • • • 0 • • 0 • 0 •
.
.
.
• • •• • 0
• 0 • • 0 •
.
.
.
.
.
.
.
.
.
O O o
vii PAGE 4.1 4.1 4.2 4.3 4.4 4.5 4.8 5.1 5.1
5 • 2 5 • 2
5 . 3
5.4
5.6
5 • 7 5 • 9
5.11
6.1
6.1
6. 2
6 . 9
6.12
6 • .15
6.16
6.17
viii
T
ABLE OF CONTENTS
( c.o n-tinue.d)PAGE
§ 8 .
SYSTE
M MONITOR
Introduction 0 0 0 • • 0
.
.
.
0 • •.
.
.
8.1 System Layout.
.
. .
.
.
.
.
.
.
.
.
0 0 0 8.1 Disc/Core Swapping 0 0 0 0 0 0 • 0 •
.
.
.
80 3 Relocation • • 0
.
.
. .
.
.
• • 0
.
. .
8 . 3 System Modes.
.
.
• • 0.
.
.
. . .
.
.
.
8 . 4 Interrupt Servicing • • 0. .
. .
.
.
.
.
.
8 . 5 Monitor Status.
.
.
0 0 0 0 • •.
. . .
.
.
8 . 7 Test Module Generation.
.
.
.
. .
.
.
.
8 . 8 Monitor Core Layout • 0 •.
.
.
.
.
.
.
.
.
8 0 9
Monitor Resident Routines
. .
.
0 0 0 8.10 Spooler • • 0 0 0 0.
.
. . . .
.
. . .
.
.
8 .12
Time Scheduling • • 0 0 • • • • 0
.
.
.
8.13Program Executive • 0 • 0 • • • 0 •
.
.
.
8.15 Event Scheduling 0 0 0.
.
.
.
. .
.
. .
8 . 18Monitor Routines • 0 • • 0 • 0 • •
.
.
.
8.22§ 9 0
SYST
EM
E
XTEN
S
ION
Introduction
.
.
.
• 0 • 0 0 0 0 • •.
.
.
9.1 Terminal Packages 0 0 0.
. .
.
.
.
• • a 9. 1
1.1
CHAPTER 1
INTRODUCTION
1.1 Maehine Ha~dwa~e
This work describes software development undertaken on a DDP-516 general purpose digital
computer. The central objective is a time-sharing operating system capable of supporting interactive
computing facilities between the central processor and eight remote keyboard terminalso
The installation used for software development was equipped with the following hardware:
(i) Central processor.
(ii)
(iii)
DDP-516 single address binary word
computer; 16 bit word size;
.
• 9 6 µsecmemory cycle time. 16,384 words
(32 Kbytes) of magnetic core storage, addressable in sectors of 512 words. Single index register (X).
Standard inter~upt line. Main frame options.
(a) Direct multiplex control (DMC) for data transfer between core and peripherals parallel with computation.
(b) High-Speed arithmetic unit for 32 bit arithmetic and double word fetch/store operationso
.
in
(c) Memory lockout provides memory bound protection registers and privileged
instruction traps; adds 6-bit J-register for base sector relocationo
(d) Real time clock (RTC) provides a 50 Hz clock with standard interrupt capability. Automatic incrementation of dedicated
memory location. Peripher·als o
10 surface moving head disc units (2) 300 1pm line printer
450 cpm card reader
1.2
The on-line disc equipment is described in Chapter 5.
Disc, printer, and card reader controllers are equipped
with DMC channels. The multiline controller and line
terminating units for the teletype terminals are
described in Chapter 2.
The instruction repertoire of the machine is
set out in [l], and is seen to be largely a standard instruction set for a single address binary computer.
Features worthy of note are:
(a) the byte manipulating instructions which
confer fast string manipulation power.
(b) the compare and skip instruction (CAS) which provides a three way branch on comparison.
(c) the increment, replace and skip instruction
(IRS), which permits the use of any core
location as dn increment counter with overflow
t est and skip capability.
Machine instructions can be grouped into four
categories by struc ure:
(a)
(c)
generic
shift
(b) memory reference
(d) input/output
(a) and (c) have 16 bit formats. Memory reference
instructions have a 9-bit address field. The format is:
1 2 3 4 5 6 7
I
8I
9!10
I
l l
I
12I
13!
llf115 116
'
\'
\ '- ~ -'L~eator
-.r~
operation addr>ess
code bit
tag bit {index bit)
la
f g hit {indirect hit)
Any instruction can thus reference one of two 512 word
sectors: ( i) the sector in which the instruction is
.
stored, indicated by the sector bit set (ii) the basesector, indicated by the sector bit reset. Inter sector
references must be made via the index register, or
indirectly via address
.
constants stored usually in the base sector.I
1.3
Input/output instructions are formatted as:
3
I
4 '
s
I
6
17
I
8I
9110
I
11I
12 '13
I
14115
'161
L.._ _ _ _ _ _ _ , ~ - - - ' ' - ' - - - . v ""v'" . / ' · . . . _
-operation function deviae
address
code field
The function field, bits 7-10, is used to differentiate between various interface functions to control a
peripheral device. eg see listing 6 page 4 for the
OCP functions for ·he disc controller. The input (INA)
and output (OTA) instructions for data transfer via the I/0 bus incorporate a "ready" status check on the
addressed peripheral. If the "ready" is true the word
transfer proceeds, and an instruction skip is executed. Otherwise, no data is transferred, and control passes to the immediate subsequent instruction.
1 • 3 C a n v e.. n:t i a nl>
is DAP- 16 .
The assembly language used throughout the text The instruction mnemonics and assembly
pseudos are summarized in [l]. The listings appended
to a number of chapters were produced by a FORTRAN program
which processes assembler output o
The seven field format for these listings is:
.
line number, oc al address, core image (format varies with instruction category), address tag, operationmnemonic or pseudo, reference address, comment. Pages are sequence numbered for each listingu Listings are referenced by (pN/M _ for page N line M, and refer to the listing appended to the chapter in which the reference is madeo
Other conventions used in the text include: [LOCN] indicates the contents of the core location at address LOCNo
(X) indicates the contents of a hardware register, typically the index register.
LOCN (X} indicates the address formed by dis-placement from LOCN by (X).
1.4
The aims of the system design for machine
usage are seen to require four distinct tasks. These
are the development of:
(i) Software for multi-user interactive processing.
(ii) A general purpose processor for disc based
files to support interactive and batch
operations.
(iii)
(iv)
An interrupt driven batch input-output spooler
as background of (i)o
The interfacing of automatic programming
systems and common user packages to (i) and
(ii) 0
This work deals in detail with (i), with only
brief references to the other tasks where relevant to the
discussion " (i) is seen as framework of routines upon which the remainder are built. It consists of a number
of distinct parts:
(i) A terminal buffer driver which will support
record input/output independent of the current
status of the target program.
(ii)
(iii)
A driver for the on-line disc storage devices
which will service the needs .of batch and
interactive machine usageo
A time share monitor for multi-user scheduling
and controlo This must also service user
requests for monitor functions.
For development purposes, two interactive
terminals were interfaced to the central processoro The
machine core storage was consictL ~d to be partitioned
into four parts, each of 8 Kbytes, assigned to;
(1) monitor and driver routines, (2) file processor and spooler, and (3) two user modules which would alternate
between execution and core-disc swappingo The system
implementation proposed envisages expansion to eight
2.1
CHAPTER
Z
CHARACTER INPUT-OUTPUT
Z
.
1
Int~oduet~on
This section outlines the driver routine which is used to input/output characters for keyboard terminals.
The routine is coded to drive eight 110 baud asynchronous lines which transmit characters serially at 11 bits per
charactero Input/output is via a multiline controller which is equipped with one input gate and one output bit buffer per line, and a clock interrupt running at eight times the line baud rate. The transmission system is blind, full
duplex with the driver routine providing echo output of all character input. A full program listing of the driver
routine is included in this chapter to facilitate discussion, and references are made throughout the text to this listing by means of page and line number.
Z.
2
TheMultiline Cant~olle~
On-line keyboard terminals are connected to the
central processor via the multiline controller. The controller decodes the address and function field bits of an input/
output instruction as for all peripheral controllers using the
input/output bus mode of data transfer. The controller lS . capable of handling up to eight groups each of 16 lines interfaced to a line terminating unit. With a single line
terminat ing unit for the 16 lines of group 0, two input/ output instructions are available (3].
INA '1044 is used to input to the A-register the current line status of the 16 lines, each bit position in
the A-register corresponding to one line, with bit position 1 corresponding to the lowest line number, i . e . , line 0. Any line which is spacing will set the corresponding bit in the A-register, a marking line leaves the A-register bit reset.
If any line i~ spacing, the device ready line is set by the
/
2 0 2
OCP '44 is used to output from the A- register the
required output line status of the 16 lines, each bit position
in the A-register corresponding to one line, with bit position l
corresponding to line
0.
Bits set in the A-register initializeor continue line spacing, bits reset cause line marking.
The line logic levels are:
logical
0
= line spacinglogical l = line marking
The basic line interface consists of a single gate
for input and a single bit output buffer for each line . A line
terminating unit comprises interfaces for 16 lines. Figure 2-1
shows a simplified logic schematic for the line terminating
unit. When the INA instruction is decoded by the controller,
the derived signal gates the input line status to the A-register
via the input bus. The resultant A-register status is the
complement of the line logic levels. For output, the complement
of the required status for each line is loaded into the
A-register and the OCP instruction executed. The controller
decodes the OCP to strobe the contents of the A-register into
the respective output flip-flops.
In addition to st~ndard I/0 instruction decode
logic, the multiline controller contains a high speed clock
which can be enabled to generate standard central processor
interrupts at eight times the line ·bit rate, and the normal
peripheral mask flip-flop which can be set to enable such
interrupts. The instructions available to control the
multiline controller clock are: SMK '420 which sets the
clock mask, and thus enables clock interrupts at a frequen cy
of 880/second. This mask flip-flop is not reset by the normal
peripheral SMK '20 instruction; OTA '54 - skip i f multiline
controller clock ready and mask set, which enables the clock
interrupt to be identified. The clock ready condition
generates an interrupt signal on the standard interrupt line,
forcing JST* '63 i f the central processor is in enable mode.
2.3 The V~ive~ Routine
The character input/output driver (CIOD) rout ine
uses the clock interrupts to synchronize the execution of INA
and OCP instructions to the line speed. The output line bit
1 - SPACE
OUTPUT BUS
0 -
MAROCP
1 A-REGISTER 6
1
¢ = MARK
,i
-- SPAC
INPUT
BUS
INA
LINE TERMINATING UNIT
FIGURE
2-1
1
LINE 0
0 = SPACE!
1 = MARK
LINE 15
LINE 15
0 -- SPACE
I
IN~UT LINES
I
I
1 -- MARK2.4
scheduled at 110/second. The INA instruction is scheduled at 440/second, ie, at four times the line rate of 110 baud. It is not necessary to use the maximum clock frequency of 880/second
to achieve acceptable accuracy because of the proximity of the keyboard terminal sites to the central processor and the
. consequent low transmission distortion. The development version of the driver uses a software method of bypassing alternate
interrupts, but this will be replaced in favour of hardware
modification of the clock interrupt frequency when the hardware development is complete, providing i t can be verified that
the line signal distortion is within acceptable limits which will enable input sampling at four times the bit rate.
The origin of all standard interrupts is identified
by the monitor and control passes to CIOD when the multiline controller clock verifies as the interrupt source. Since the CIOD routines are lengthy, they must run with disc interrupts
enabled to ensure consecutive record handling by the disc
driver. All other drivers are disabled by CIOD before the
CPU is restored to interrupt enable mode (listing 2 - p3/79-81).
The maximum interrupt disable time for the routine is 30 µsec, which is within the limitation set by the disc driver for
continuous record access, and can be substantially reduced . by
hardware halving of the clock interrupt frequency.
2.4 Routine Seheduling
The process of input/output of serial bit strings from terminal lines and the construction/serialization of
half word bytes, is accomplished by a series of five routines which use a number of core tables . The relationship between the routines and the tables they process is shown schematically
in figure 2-2. The routines are :
INPUT: which schedules the input INA and deposits the
successive entries in the sample data table .
EXTRACT: which searches for , identifies and extracts
characters from the entries in the sample data table,
and packs them in the compressed character table.
CONSTRUCT: which rotates serial strings packed in the
compressed character table to form half-word bytes and
HARDWARE INTERFACE
INPUT
,'< 1 1 A-REGISTER
LINES
SADT
SAMPLE
DATA
TABLE
EXTRACT
t
SAMPLE SWITCH
TABLE
SSWT
OUTT
CHARACTER
DRIVER
CMCT
COMPRESSED
CHARACTER
TABLE
I :::-:::,,<CONSTRUCTI =::>I
OSWT OUTPUT SWITCH TABLE
LOCH
LINE
LICH
LINE
INPUT
CHARACTER TABLE
ECHO
BUFFER DRIVER
BUFFER INPUT
[LINE BUFFER
OUTPUT OUTPUT
TABLE K"= <4,:: ER IA LIZ El'< I
c
HAR ACT ER OUTPUT1-<
i
( BUFFEROUTPUT TABLE
CHARACTER PROCESSING THROUGH VRIVER TABLES
FIGURE 2-2
N 0
2 • 6
SERIALIZE: which accepts character inputs from the line
output character table and rotates them from byte to
serial bit form in the output table.
OUTPUT: which schedules the output OCP to set the line bit
buffers using the successive entries in the output table.
The scheduling of these routines over the bit
transmission interval of approximately 9.1 milliseconds lS
.
shown in figure 2-3. As illustrated the input routine is
schedul6d at a frequency of 440/second , while each of the other
routines is scheduled at 110/second , ie, once per bit intervalo
By scheduling the routines in this manner the processing
required on the occurrence of each clock interrupt can be
completed before the occurrence of the next clock interrupt,
so that interrupt-on-interrupt processing, requiring a push
down stack for the saving of machine status and interrupt
returns, is not necessary. This is a considerable economy
but gives the driver an upper limit characteristic for the
number of lines which can be handled. The maximum available
time for each rout ine is 2272 microseconds which is effectively
reduced if the direct multiplex controller is
using program breaks for disc I/0 transfers.
concurrently
The usage of this
scheduling interval by each routine is considered later under
character driver timing.
2 • 5
The driver routines interract via the following core 1:ables:
SADT: The sample data table which stores the successive
samples of the line status input by the INA instructiono
This table has a capacity of 64 words and can thus store
16 bits at 4 samples per bit fr om each of the 16 po~sible
input lines .
SSWT: the sample switch table has one entry corresponding
to each 4 entries (samples of 1 bit) in the sample data
tab le . This table is used to switch the status ~t the
sample table to "possible new activity" after charc.1.,....,+er
extraction has been completed.
DUTT: the output table which contains the successive line
buffer settings to be output at bit rate intervals. These
are the bit series for line output characters toge~her
with appropriate control bits. The table has capacity
2272 µsecs
EXTRACT
INPUT
9.1 msecs
SERIALIZE
INPUT
-->~~<---
INTERRUPTDISABLE
3.0 ·µsecs
CONSTRUCT
INPUT
SCHEDULING OF CHARACTER VRIVER
ROUTINES
FIGURE 2-3
~ - C I
ECHO
bUTPUT
INPUT INTERRUPT SKIP ,
INTERRUPT DISABLE
12 µsecs
l'0
2. 8
OSWT: the output switch table which contains one entry
for each entry in the output table . This table is used
to switch the line output status to ready when character
transmission is completed.
LICH: the line input character table which has a capacity
for 16 characters. This table consis~s of the characters
from all input lines in the order of their arrival, each
with originating line identification . This is the
character driver output to the buffer dr)iver rout~n~so
LOCH: the line output character table which has a capacity
of one character for each line to be serviced by the
driver. Characters to be output to a given line
are deposited by the buffer driver routines 1n a
table entry specific to the line. The output ~ine
is identified by the position in t he tableo
CMCT: the compressed character table which contains all
the characters which have been input starting in the
same bit period. All extracted characters are compressed,
without stop bits, and such that the ir start bits are
contained in the first word of this tableo
These tables have the following common characteristics:
(1) they are circular (except CMCT and LOCH) and their
information content must be processed within cl
specified time limit before peing overwritten" The
routine scheduling ensures no data loss,
(2) they are referenced by a series of base address
pointers which are tagged for table reference via
the index register (except CMCT) . The memory
reference to table entries is indirect with post
indexing and as such the CIOD routine must run with
extended addressing disabled.
In discussing the detailed i nteraction between tr.e
various data and control tables and the input routines, i t ~i l
be informative to consider the processing of an input example.
The character input format is: Start bit of 1 space (logic 0);
8 data bits beginning (even parity wit h the least significant
ASCII encoding); Stop bits of 2 marks (logic 1).
The line dormant condition is marking, so that an open line ls
LINE 0
1
0
START
1
0
LINE 3
I
i
1 I
~
-l
___
_
START 1
LINE 5
I
START
LINE 6
1
CHARACTER "A"
f
CHAR1
CTER "2"
I
r
0 1
CHA ACTER "Q"
iCHAR CTER "Li"
I
I
1 0
_
)
.l
I
11
l,
___.
1
SAMFLE POINTS
t
t = 0
LINE LOGIC LEVELS - 5 LINES
- - · - - - -- -
-FIGURE 2- 4
MARK
I
SPACESTOP
MARK
. I
MSPACE
l STOP
MARK
S ACE
rv:lRK
I
I... 1Aci
1 ST';P
line logic status with 4 lines active and 1 line open from
8 connected lines [2] .
The inputs illustrated in this figure are:
(i) line
0
-
character "A" Even parity ASCII - 1018Serial bindry - 10000010
(ii)
(iii)
(iv)
(v)
line 2 - character "2" Even parity ASCII - 262s
Serial binary - 010011¢1
line 3 - open - continuous spacing
line 5 - character "Q" Even parity ASCII - 321 8
Serial binary 10001011
line 6 - "Space" Even parity ASCII - 240s
Serial binary - 00000101
All other lines are marking. Unconnected lines are continuo~sly
open. For the purposes of illustration all characters are
starting i~ the same bit time, the character starts on lines 2
and 6 coinciding at the 3rd sample pointo
After 44 operations of the input routine from t ~
0
the sample table for this input stream will be as shown in
figure 2-5. Note that the sample table entries are the line
status complements, ie, bits set in the sample table correspond
to spacing lines and may indicate a character starting; bits
reset indicate that the corresponding line was marking at the
time of sampling.
2.7 Ext~aQt Routine
While input line samples are being stored, the extract
routine examines the sample table at a point lagging the
inserti on point sufficiently to ensure that on detection of a
character start the whole character will be able to be extracted
from the sample table . On being s cheduled , the extract routine,
using a sample switch table pointer derived from the sample data
table pointer, amends as necessary the poss ible new activity
mask PNAM, by switching on those l i nes (setting the corresponding
bits i n PNAM) which have had previous character input bJt for
which the sample table start-search process has passed beyond
the final stop bit of the most recent character input. Note the
initialization of PNAM to the value of CLIN (connected lines
-p25/591) after an initial delay of 11 bit intervals. This
ensures the correct time separation of sample insertion and
1
0
0 1 0 0 0 0 1 1-1 0
t
1 0 0 0 0 - 1 1-1 0 1 1 0 0 1 0 1 1
-1 tJ 1 1 0 1 1 0 1 1
-0 0 1 1 0 1 1 ~ 1 1
-0 tJ 1 1 0 1 1 ~ 1 1
-tJ 0 1 1 0 1 1 0 1 1
-k1 f1 1 1 tJ 0 1 tJ 1 1
-1 tJ 1 1 0 0 1 0 1 1
-1 0 1 1 0 rj 1 0 1 1
-1 0
i
1 0 0 1 0 1 1-0 -0 0 - 0
1 1 1 1 1 1
-1 0 () 1 () 1 1 0 1 1
-1 0 0 1 (j 1 1 0 1 1
-1 0 1 1 0 1 1 0 1 1
-(j 0
-
01 1 1 1 1 1 1
-1 0 1 1 0 1 1 0 1 1
-1 rj 1 1 0 1 1 0 1 1
-rj
-
rj-
rj1 1 1 1 1 1 1
-0 0
-
01 1 1 1 1 1 1
-1 0 1 1 0 1 1 0 1 1
-1
0
1 1 0 1 1 0 l 1-1 0
0
1 0 1 1 0 1 1-1 0 0 1 0
0
1 0 1 1-1 0 0 1 0 0 1 0 1 1
-1 0 0 1 0 0 1 0 1 1
-1 (j
?
1 (j (J?
0 1 1-1 () () -1 rJ 1 0 rJ 1 1
-( ) -( ) -( j l rJ 1 0 0 1 1 -() -()
0
1 (j 1 r:J r:J 1 1-(j 0 1 1 rj 1 1 0 1 1
-() () 1 1 () () 1 (j 1 1
-1 () 1 1 () () 1 0 1 1
-1 () -1 -1 () () -1 0 1 1
-1 () () 1 () () () () 1 1
-1 () () 1 () () () () 1 1
-() -() -() 1 () () () () 1 1
-() ()
:l
1 () () (J () l 1-0 0 0 1 0 0 0 0 1 1
-0 -0 -0 1 0 0 0 0 1 1
-() 0 () 1 0 0 0 9' 1 1
-0 -0 0 1 0 0 0 0 1 1
-91 0 0 1 9' 0 0 0 1 1
-() 9' () 1 0 0 0 0 1 1
-SAMPLE VATA TABLE
FIGURE 2-5
2.11
-
--
--
--
-2.12
for all lines.
in this case.
The test at p6/159 cancel s the scheduled search
This has the effe ct of making the i ncrement in
machine time required for activity on the last connected line
very small.
In the example under consideration:
[PNAM] = 1111111100
and a sample search is thus called for, using this word copied
to SMSK (new starts mask) as a mask to detect start spaces
(bits set). An examination of the first sample,
[SADT(SPTR - 44)] A [SMSK]
indicates possible character starts on lines
0
and 3. Thedetection of at least one start bit passes control to
CONF (pB/180) where the above starts word is stored at SRTS
(sample starts). The pointer to the start-search is saved
and the start is confirmed by comparing the third sample of
the start bit with the first sample.
[MSTX] + [SPTR] - 42
[SRTS] + [SRTS] A [SADT(MSTX)]
A zero match will cancel the extract routine, but for the example:
SRTS 1001000000
---and the stop bits must be examined to verify the presence of a
character. The table pointer (X-register) is advanced by
36 samples to the first stop bit - third sample, and any line
which has spacing samples (indicating an open line) is removed
from further consideration in start-searching by:
(X) + [MSTX] + 36
[SMSK] + [SADT(X)] A [SRTS] ~ [SMSK]
and from character extraction by:
[SRTS] + [SRTS] A [SMSK]
Since true characters on a line are indicated by corresponding
bits reset at SADT( SPTR - 42 + 36), the mid stop bit sample,
only those lines with true character starts will survive this
Finally, these lines are excluded from further starts
searching by:
[SMSK] + [SRTS] ~ [SMSK]
For the input example we have then at p9/210:
[SMSK] = 0110111100
[SRTS] = 1000000000
2.13
and the character from line 0 will then be extracted from the
sample data table and compressed into CMCT (the compressed
character table), being merged in CMCT with any characters
extracted previously, but in the same bit time.
[CMCT] + [SRTS] V [CMCT]
[CMCT + n] + [SADT(MSTX + 4n)] A [SRTS] V [CMCT + n]
n = 1, 8 for the 8 data bits.
The third sample of each input bit is used for the character
extraction. This r esults in the compressed character table,
which is zero filled on entry to the extract routine, as
illustrated in figure 2-6(a).
As only one sample has been examined for the occurrence
of a character start, control now returns to NEXS (p7/172) and
the sample table pointer advanced to the next sample. Note that
the IRS 0 instruction may be used at NEXT+ 1 (p9/230) since
the table pointer cannot wrap around the table in the four
start-search entries. SMSK, as continuously updated, is thus
used to look at each table entry
[SADT(X)], (X) + [SPTR] - 44 + n, n - 1 4
'
In the case n = 2,
[SADT(X)] A [SMSK] = 0
and no character extraction is processed, control passing to
NEXT+ 1 (p9/230) . The third start-search sample reveals the
presence of possible starts on lines 2 and 6:
[SADT(SPTR - 41)] A [SMSK] = 0010001000
which verify as true characters and set:
2.14
The compress routine extracts the line 2 and 6 characters in
.
parallel (both lines set in SRTS) and merges trem in CMCT with
the result illustrated in figure 2-6(b). The s,art-search
continues with the fourth sample at [SADT(~F~R - 40)] and the
character from line 5 is compressed with:
[SRTS] = 0000010000
--The resultant compressed character table when the start-search
sample tally has incremented to 0 (p9/233) is shown in
figure 2-6(c). The table base at CMCT is now set in all bit
positions for lines which have yielded a character in the last
bit time. If this is non-zero, i t can be entered in the sample
switch table, for use at a bit time one character in advance
of the current extract pointer.
(X) + {[SPTR]/4 + 10} mod 16
[SSWT(X)] + [CMCT]
[PNAM] + [PNAM] ~ [CMCT]
The final operation is to remove all lines which have just
yielded characters from any consideration as sources of
possible new character starts until the elapse of the remainder
of one character time, at which time the entry in the switch table will restore them to "possible" status by setting the
corresponding bits in PNAM (see beginning of extract routine
at p6/156-158).
The construct routine is scheduled once per bit time
lagging the extract routine by one half a bit time. The r r~ 1 t 1 n •
continuously examines the base of the CMCT table for dny
indication of deposit by the extr~ct routine. If there i~ no
input, the routine re urns from the interrupt (plJ/26~). When
CMCT contains at least one bit set, the table will contain
an input character, one bit. per table entry with the lects,
significant bit in the lowest table entry, CMCT + 1. The line
which originated the character will be indicated by the bit
position in the table which the character occupies (see
figure 2-6). CMCT is shifted left one bit at a time to detect
the occurrence of the start bit (pll/269), while a counter,
l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l 0 0 0 0 0 0 0 0 0 0 0 0 ~ 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
( a 1
AFTER LINE
¢EXTRACTION
l 0 1 0 0 0 1 0 0 0 0 0 0 0 0
0 0 l 0 0 0 l 0 0 0 0 0 0 0 0 1 0 0 0 0 0 l 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 l 0 0 0 l 0 0 0 0 0 0 0 0
1 0 0 0 0 0 l 0 0 0 0 0 0 0 0 l 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 l 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
( b )
CHARACTERS MERGEV
FROM
LINES 2 and
6l 0 l 0 0 l l 0 0 0 0 0 0 0
0 0 l 0 0 0 1 0 0 0 0 0 0 .0
l 0 0 0 0 1 l 0 0 0 0 0 0 0
l 0 1 0 0 1 l 0 0 0 0 0 0 0
1 0 l 0 0 l 1 0 0 0 0 0 0 0
1 0 0 0 0 0 ..L , 0 0 0 0 0 0 0
l 0 0 0 0 1 0 0 0 0 0 0 0 0
0 0 l 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
( C. )
ALL
INPUT
CHARACTERS
STARTING IN THE SAME
BIT TIME
COMPRESSEV CHARACTER
TABLE
FIGURE 2-6
0 0 0 0 0
0
0 0 0
0 0 0 0 0 0 0 0 0
0 0
0 0
0 0 0 0 0
2.16
When the start bit is detected, (sign bi~ set 1n
.
c ft r· o tat e dcharacter marker at CMCT) the line number is used as an index
to the bit position table to extract the apTropr iate bit mask
for the line, BMSK (pl2/296).
The routine CON4 (pl3/305) thrr irocesses the eight
compressed table entries to copy the ser,. ll bit -pattern into
a work location CDEP (character deposit ). The bit string is
shifted into CDEP from the left so that the least signiricant
character bit is now occupying the least significant byte
position. A parity counter is incremented for each bit set
in the character. At the completion of rotation the byte
occupies bits 2-9 of CDEP. The input character "rubout"
(or "delete")= 377g even parity ASCII, can be bypassed at
this point, as i t results in CDEP = 0 (pl3/317). Odd pdri~y
input is replaced by the character "t" = 336 8 . The character
is positioned in the left byte (bits 1-8) with bit l set for
internal ASCII format, and the originating line number is merged
into the right byte (pl3/325) . The operation
[CDEP] +~ [LICH(IPTR)]
completes the process by storing the input character in the
next available entry in line input character table and ~iEaring
the work location. The LICH table pointer is then ctdvan E::i .... d. 1,J
the construct routine recycled (pl4/33 9) until all entrie~ in
CMCT have been processed . When this is so, (pll/2'/3) th
counter for the line number is restored to zero and the
compressed character table is cleared for use by the next
scheduled extract operation. Figure 2-7 shows the po.r·t ion of
the LICH table generated by the input example shown in
fig u r e 2 - 6 ( c ) , and i 11 us t. rat e s t he st or age f or mat for 1: h i
table.
1 1 0 0 0 0 0 l. 0 0 0 0 0 0 0 0 = II A II LINE 0
1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 -= II 2 II LINE 2
1 1 0 1 0 0 0 l 0 0 0 0 0 l 0 1 -· II Q II LINE 5
1 0 l 0 0 0 0 0 0 0 0 0 0 1 1 0 -= II b, II LINE 6
0 0 ¢ 0 0 0 0 0 0 0 0 0 0 0 0 0 = READY
LINE INPUT CHARACTER TABLE
2.17
Figure 2-8 is a simplified illustration of the
character input process showing the da ta flow thr~ugh the
tables of the character driver, and the seq1..1.t!nce of three
forms taken by input characters during the rvo~ess.
For the purposes of disc ussioc ct series of characters
to be output to terminals is i l lus t rated in figure 2-g(ci),
This shows the contents of the l ine output charactet' t<l~:e
(LOCH) which has been set up by the l ine buffer driver. rne
format of the table is:
Bit 1 set to indicate out put character ready"
Bits 9-16 output character in ASCII encoding"
The line number on which the chara ct er i~ ~o be output i~
indicated by the position of the character in the tdble.
The table illustrated thus contains:
character 11811
for output to line 1
character 11
4 11 for out put to line
3
ch a r act er• 11
? 11 for output t o
1 in e 7 .
The line output format to be generdted for edch
character is a serial b i t string consisting of: Start b"t f
1 spac e. (logic 0) ; 8 data bits beginning with the le~ t
significant (even parity ASCII) ; St·op bi+s of 2 mark3. (lngic 1).
A do r• man t output 1 in e mu,.;) . · be con t L nu o us 1 y b P l tl in
the marking state.
2. 10 S~nialize Routine
Characters from the LOCH table mast be serid~ize~
for transmission to line, bit s trings be~ng stored ~n ln~
circular output table OUTT. ThiB table has capaci·ty tor
16 b its for each connected line . The seridlize r~utine i r ' ... .., .
searches the LOCH table in line order, detecting tt~ pre En e
of an output character by the s ign b it (pl5/365). When L l
.
~detected, the bit ma sk for the r equ1Peri l1ne is ext.rd ·tel rtnd
first used to examine the ready status of the line (~lf/,7J)
The flag word LRST (line ready status) has the a ppropriately
positioned bit reset i f a line is busy, ie, i f the output •ctble
already contai.ns a bit string f or the line for which trans ls~ion
has not been completed.
continues (pl6/381).
0
I
i
(SAMPLED FORM)
2 3 5 6
l l
l
l
ACTIVE
INPUT LINES
I
A-REGISTER=
~ ~
i
LINESTATUS
SAMPLES
}
--
---INPUT
\
START-\ SE:RCH
(SERIAL BIT FORM )
CONSTRUC
(BYTE FORM)
:rSCII
LICH
,i\ I
LSBI :
0
2
r
IPTR
5
f
6
I j
-
t -.-.-, -
---=-~
ORIGINATING LINE NUMBER
I . i
A]l)T
I
SPTRI
b
t
-0 2 3 5 6
l
HARACTER
0 2 5 6
CHARACTER INPUT PROCESSING
FIGURE 2-8
BITS
~ = B I T SET= CHARACTER START
LSB = LEAST SIGNIFICANT BIT
t0
.
I-'2.19
When a ready line is detected, i t is set busy and
the LOCH entry cleared, having been copied, minus the sign bit,
to the working store RCHR (rotation character) (pl6/374-5).
The next OUTT entry to be transmitted is set at the required
line position to transmit the character start pulse. achieved by (pl7/406-8)
[OUTT(OPTR)] + [OUTT(OPTR)] V [BMSK]
This is
The OUTT pointer is incremented and successive bits of RCHR
examined in the low order bit position by right shifts. If
reset, the above logic is again used to set the output table
to space, otherwise the OUTT pointer is moved on, as the
normal condition for the OUTT entries is zero, corresponding to line marks. This process (pl7/400-3) ensures the
serialization, complementation and correct serial ordering
required for line output format. A parity count is accummulated during the shift process and if odd, the most significant
character bit is reset for even parity output.
No entries need to be made in the output table for
the stop bits, since OUTT entries are cleared on transmission
to return the line to the marking condition. Figure 2-9(b)
shows the condition of the output table at the completion of
the serialization process. Note the complementation of the
entries to ready for the NAND operation of the OCP instruction,
and the synchronization of the three· start bits. The serialize
routine is limited in such synchronization to a total of four
characters because the time required to service more is near
the limit o f \ the bit interval less allowance for parallel
DMC operations" The maximum delay with 8 connected lines
would be 1 bit time with all LOCH entries simultaneously
ready.
As the rotation of each character is completed, the
routine RSTR (pl8/422) is entered to set the output switch
table by:
[OSWT(OPTR + 10)] + [OSWT(OPTR + 10] V [BMSK]
This marks the corresponding entry in the output table (the
second stop mark) at ·er the transmission of which the line
2.20
LINE NO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 l l 0 1 0 0 l l 323 8 = II
s
II2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 l 0 0 0 0 0 0 0 1 0 l l 0 1 0 0 254 8 = II 4 11
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 l 0 0 0 0 0 0 0 1 0 l l l l l l 277 8 = 11 ?11
(a)
LINE OUTPUT CHARACTER TABLE SHOWING OUTPUT
EXAMPLE
0 0 0 0 - 0 0 0 0 0 - 0 0 0 0 0 0 0
start space 0 l 0 l 0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 ·1
0 0 0 0 0 0 0 0 0 0 0 0
..L.
0 0 0 l 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 data bits 0 l 0 l 0 0 0 0 0 0 0 0 0 0 0 0
(even parity1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 l 0 0 0 1 0 0 0 0 0 0 0 0
0 l 0 0 0 0 0 l 0 0 0 0 0 0 0 0
stop marks 0 0 0 0 0 0 0 0. 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0 0 0 0 00
0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 ¢ 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(b)
RESULTANT OUTPUT TABLE
AFTER SERIALIZE ROUTINE
OUTPUT
TABLES
2.21
2 • 1 1 Output Routine.
The output routine, which lags the serialize routine
by
t
bit time, deposits the output table entries in the outputline bit buffers and clears the entries to reinitialize the
table. It then clears and extracts the line ready status
switches from the output switch table . A l ine £or which a
character is entered in OUTT will be kept in the busy status
(corresponding bit of LRST reset) for the character transmission
interval. After the advance of OPTR (the output table pointer)
to the final stop bit, and the completion of the OCP instruction
for the corresponding table entry, the line status is set to
ready by:
[LRST] + [OSWT(OPTR)] V [LRST]
The table pointer is now advanced (the table is cyclic) so
that, on the next schedule of the serialize routine, a new
character start may be generated for any line for which
transmiss ion of the table entries has now been completed.
Figure 2-10 illustrates the movement of characters through the
output tables for transmission to line.
2 • 1 2 Ee.ho Routine..
The terminal teleprinters are operated in blind,
full duplex mode, that is, the keybqard inputs are not locally
.
communicated to the output printer. All legitimate keyboard
input is required to be echoed, and certain input characters are
used for control. purposes . The line buffer dr1iver (e;hapter 3)
maintains status flags for the current line mode (input/output)
which depends f~om time to time on the demands of the system/user
program being currently controlled from ~he terminal. If the
output mode is current, all output is being generated by the
CPU, and input is not legitimate. Provided then that the
output mode is not set, the echo routine transfers input
characters from the line i nput character table to the appropriate
entry in the line output character table. The foll wing
characters are trapped by the process for special action.
$ This character is used as a keyboard interrupt
charact er for any mode (input/outp...1.+-,/compute)
and as such it is the only input recognized i f
OUTPUT
1
LSB ~
-8 DATA
BITS
LSB
1 3 7
2.22
ACTIVE OUTPUT LINES
t
t
t
1 - - - - = - - - ! - -_ __ . . . L _ _ - -
-A-REGISTEk
-
--- OUTT
<-~
~
~
- -
-
START-·17
__
~
LPTR
~- --
-STOP
- -
-
MARKS-- -- - -
-~
I\
A
Ii\
-
-LOCH
i
3~
'7 ~
~
8 DATA
L INE NO OF DESTINATION
r - - · - -- - - 4 - + -- - - - '
-y1
'
BITS I \
~=BIT ERIALIZ
LSB-=LEAS BIT
CHARACTER OUTPUT PROCESSING
FIGURE 'Z-10
SET L;r1\R. BIT
T (
1'l a 'At'T