A Morphological array image processor controller chip set

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2-1-1997

A Morphological array image processor controller

chip set

Christopher Insalaco

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A MORPHOLOGICAL ARRAY IMAGE

PROCESSOR CONTROLLER CHIP SET

by

Christopher

J.

Insalaco

A thesis submitted

In

partial fulfillment of the

requirements for the degree of

Master of Science

In

Computer Engineering

Approved by: Prof.

_

George A. Brown, Thesis Advisor

Prof.

_

Robert E. Pearson

Prof.

_

Roy S. Czernikowski, Department Head

Department of Computer Engineering

College of Engineering

Rochester Institute of Technology

Rochester, N ew York

A MORPHOLOGICAL ARRAY

IMAGE PROCESSOR

CONTROLLER CHIP SET

I Christopher

J.

Insalaco hereby

grant permission

to the Wallace Library of

the Rochester Institute of Technology to reproduce my thesis

in

whole or

in

part. Any reproduction

will not be for commercial use or profit.

RochesterInstituteof

Technology

Abstract

AMORPHOLOGICALARRAY IMAGEPROCESSOR CONTROLLERCHIP SET

by

ChristopherJ. Insalaco

The

design,

simulation andlayout of a controller _chip set for a morphological

array image processor shall be discussed. These VLSI chips in conjunction with the Morphological

Array

Processor

(MAP)

and Arithmetic Logic Unit

(ALU)

chip sets perform the morphological image

processing

operations of erosion and dilation on 512x512 _pixel, 8-bit gray scale images using a 7x7 windowingmatrixinrealtime (60 framesper second). The controller_chip set design allows for pipelining of successive MAP's as well as operation on 1024x1024 pixel,8-bit grayscaleimages.

To facilitate the

design,

additional scaleable CMOS standard

library

cells and correspondingparameterizedschematic

library

components were designedand integrated with the RIT CMOS standard cell

library

designed

by

Computer

Engineering

graduate student

Larry

Rubin as part of his Masters thesis1. In particular, additional D flip-flops with both

Q

and

Q

bar _outputs,

and-or-inverts,

or-and-inverts,

CMUXes,

and MOSIS 64 and 84 pin pad rings were created. The cells were designed to be _{fabricated using} the Metal Oxide Semiconductor Implementation System

(MOSIS)

scaleable CMOS 2.0 pm

chips were designedand sent to MOSIS for fabrication. The layoutanddesign rule verification of the final two test _chips, test chips five and _six, was

performed

by

the author. Test chip four contains a_variety ofMUXes and D

flip-flops,

test_{chip five} containsa_varietyoftransfergates andinverters.

Thecontroller _chipsetconsists ofa64pincontrol_chip

(Controller)

and an 84

pin

memory

controller _{chip (Mem_Control). The} controller chips provide the

ability to _selectively process 512x512 or 1024x1024 image sizes

by

_modifying the

pullup

or pulldown of a "size" bit. A selectable

delay

was

implemented,

through the_pullup or pulldown_setup ofthree

delay

bits,

inthe Controllerto

TABLE OF CONTENTS

ABSTRACT iii

LIST OF FIGURES vii

LIST OF TABLES ix

L INTRODUCTION 1

EL HISTORICALREVIEW 2

A. Design BeforetheLibrary 2

B. Test Chips 3

C. The Commissionof aMorphological Chip Set 5

DI.THEORY 7

A. Morphology 7

1.EUCLIDEAN MORPHOLOGY 8

2. DIGITAL MORPHOLOGY. 12

3. GRAY SCALEMORPHOLOGY 14

B. Design RuleChecking 16

IV. MATERIALSANDAPPARATUS 23

A. MentorandCadence Tools 23

B. Tektrontx Logic Verifier 27

V. METHODOF PROCEDURE 27

A.Cadence DraculaHLayout Verification Tools Setup 29

B. Additional Standard Cells 31

C Test Chips 5and6 37

D. Morphological Array Processor Controller Design 40

1. The Functional Design ArchitectureoftheMAPController

Chip

40 2. The

Top

LevelDesign_oftheMAP Controller

Chip

Set 66 3. The Logic Design oftheControllerandMemjOontrol 75 4. The Logic Simulation_oftheControllerandMemControl. 91 5. TheCircuit Design_oftheControllerandMemControl 93 6. The_{Circuit Simulation of}theControllerandMemControl 93 7. TheMorphological

Array

Processor

Top

Level Simulation 94

8. The Layout_oftheControllerandMemControl 95 9. Suggested

Testing Methodology

fortheControllerandMemControl 98

VL RESULTS 98

VHLCONCLUSIONS 102

A. Future Work 103

APPENDIX A 105

DRC.COM File 105

APPENDIXB 109

LVS.COM File 109

APPENDIXC Ill

LPE.COMFile Ill

APPENDIXD 114

Simulation Files 114

1. Start Blank Physical Simulation File 114 2.Start BlankPhysicalSimulation Results 117

3. Start BlankLogical Simulation File 118

4. StartBlankLogical Simulation Results 120

APPENDIXE 121

Layout Plots 121

REFERENCES 125

LIST OF FIGURES

Number Page

Figure1 SpacingCheck 19

Figure 2 Enclosure Check. 19

Figure 3 Transistor Overlap Check 20

Figure4Transistor Spacing Check 20

Figure5CMUX4 Schematic 32

Figure6 DLAT Schematic 33

Figure7 DLATAR Schematic 34

Figure 8 ND3_2 Schematic 35

Figure9 NR3_2 Schematic 36

Figure 10 Test_Chip_5 Schematic 38

Figure 11 Test_Chip_6 Schematic 39

Figure 12 ImageandWindow Matrices 43

Figure 13 Morphological Array Processor Architecture 44

Figure 14 Blanking Bits 48

Figure 15 Blankingpart 1 53

Figure 16 Blankingpart2 54

Figure 17 Blankingpart 3 55

Figure18Blankingpart4 56

Figure 19 Blankingpart5 57

Figure 20 Blankingpart6 58

Figure21 Blankingpart7 59

Figure 22 Blankingpart 8 60

Figure 23 Blankingpart9 61

Figure24Blankingpart10 62

Figure 25 Blankingpart11 63

Figure 26 Blankingpart12 64

Figure 27 Image_Processor Schematic 67

Figure28Controller_ChtpSchematic 79

Figure29 Controller Schematic 80

Figure30 VarJDelay Schematic 81

Figure3 1 Bus_Select Schematic 82

Figure 32 Mem_Select Schematic 83

Figure 33 StartBlankSchematic 84

Figure 34 BlankCounter Schematic 85

Figure35Mem_Control_ChipSchematic 86

Figure36Mem_Control2Schematic 87

Figure37Mem_ControlSchematic 88

Figure3 8 Mem_Counter Schematic 89

Figure 39 MUX2xl0 Schematic 90

Figure40 ControlTimingDiagram 92

Figure41 PowerRouting Architecture 97

Figure43Start_BlankLogical Simulation Output 120

Figure 44 SCCCB Layout 121

Figure 45 SCCCBA Layout 122

Figure 46 SCCCBNA Layout 123

LIST OF TABLES

Number Page

Table1Binary Plxel ValuesandTheir Decimal Equivalents 41 Table 2 Blanking Control Values For All Index Values 48

Table 3 Blanking Control Values 50

Table4Blanking Control Values

(cont'd)

51

Table 5 Controller Inputs / Outputs 69

Table 6 MemControl Inputs / Outputs 73

Table 7 WriteEnable Truth Table 77

ACKNOWLEDGMENTS

To Lindaand

Michelle,

whomakeitallworthwhile.

Theauthorwishesto thankJeffCorrell forhis

help

withthecell

library

andthe

incorporationoftheREMEDIdesignrule checkerinto theChipgraphmacros,

Shishir Ghate for his

help

with the cell

library

and ALU design and the

integration of the

library

with

Cellstation,

Jeff Hanzlik for his

help

with the

logical definition of the

MAP,

Jens

Rodenberg

for the MAP Architecture

section andthelogical design ofthe

Controller,

and

Larry

Rubin for his work

in

designing

the cell

library,

enhancing the design automation tools and the

LIST OF ABBREVIATIONS

ALU

Arithmetic

Logic Unit

CAD

Computer Aided Design

CIF Caltech IntermediateForm

CPF

Circuit Path Finder

DRC

Design Rule Checker

ERC Electrical Rule Checker

HDL Hardware Description Language

IBM International Business MachinesInc.

LPE Layout Parameter Extractor

LVS Layout Versus Schematic

LSI Large Scale Integration

MAP Morphological

Array

Processor

MOSIS MetalOxide Semiconductor Implementation System

MSI Medium ScaleIntegration

NSA National

Security

Agency

RIT Rochester Institute of

Technology

SSI Small Scale Integration

Accusim, Cellgraph, Chipgraph, Expand,

Extract,

IDEA

Station, MCIF,

Mspice, Neted, REMEDI,

and Symed are registered trademarks of Mentor

Graphics Corporation.

Dracula II isaregisteredtrademarkofCadenceInc.

I. Introduction

To verifythedesignoftheRIT CMOSstandardcell

library,

created as apartof

Larry

Rubin'sthesis

1,

_{it became necessary}to set_{up layout}verificationtools for

the MOSIS 2pmN-wellCMOS process. Itwas decidedthat theMOSIS dense

rule set wouldbeusedtoallowformorecompacteddesign layouts.

So,

a set of

rules checkers to automate the design verification for this process became

necessary. The Cadence Dracula II tool set will be used in this work;

specifically the Cadence design rule checker

(DRC),

electrical rule checker

(ERC),

layout versus schematic

(LVS),

and layout parameter extractor

(LPE)

products. A

technology

(".com")

file must be defined for the MOSIS dense rule set foreachoftheproductsintheCadencetoolset.

Additional RIT CMOS standard cellswillbe

designed,

layed_out,and verified as

necessaryto complete the morphological_array controller _chip set. Inaddition

test chips willbe layed out andsent to MOSIS for fabricationto test some of

thestandard celldesigns.

Once the verification tools and additional RIT CMOS standard cells were

defined,

they

were utilized to create amorphological _array controller _chip set for use with the morphological _array processor

(MAP)

_chip set designed

by

Larry

Rubin,

and the pre andpost _{ALU chip} set designed

by

Shishir Ghate2. The

following

arethedesigngoals forthecontroller_chip set:

1. tomatchthe

functionality

oftheACTELcontroller_{circuitry design} ofJens Rodenberg3

3. toworkinconjunctionwiththe

timing

andcontrol signals oftheMAPand

ALU

_chip sets to allowthe morphologicalimage processing operations of erosion and dilation on 512x512 or 1024x1024 pixel nine-bit _gray scale

imageswith a7x7window

4. toallowfuture designs usingthe controller andMAPtobepipelined

5. toallowfuture designsto havemorethanfour

memory

units

6. to fit the controller _chip set onto MOSIS standard 64and 84pin pad_ring chips

II. Historical Review

A.

Design Beforethe

Library

Without the RIT CMOS standard cell

library

a designer would have had to enter two different sets of schematics to do both logical and circuit level simulations. This is both inefficient and_unreliable, as there is no mechanism to_verifythelogic levelschematic withtheequivalenttransistorlevelschematic.

Another drawback of the generic logic level

library (gen_lib)

supplied

by

Mentor

Graphics,

is that _every component has a default

delay

ofzero when simulated. This is overly _optimistic, and prevents operation in systems with

feedback,

such as an SR latch. Race conditions are not _modeled, nor are

settlingglitches ofthe circuit's outputs. The

library

solves these problems

by

Before the

library

was _created, no standardized mechanism existed to _actually

fabricate designs throughtheMOSISprogram.The SPICE fileswere _obsolete,

and _overly simplified

(they

did not model leakage current or junction

capacitance) andtherewere nopadcells.

For the design and implementation of _{any VLSI project, especially if it is}

intended to be

fabricated,

the compilation of a standard

library

is not _only

practical, but a _necessary and an inevitable evolutionary stage of _{any CAD}

center.

B.

Test

Chips

At the time the RIT cell

library

was _proposed, MOSIS supported twelve

differentprocesses,

including

2.0,

1.6,

and 1.2micron CMOS and even aGaAs process. A standard ceE

library

(withno _components) available from

MOSIS,

was developed at the

University

of Mississippi for the National

Security

Agency. This cell

library

is publicly available. When the RIT cell

library

was

proposed,

Larry

Rubin designed and fabricated a test _chip to compare some

prototype cells with the equivalent cells supplied

by

the NSA to determine if

therewere_any advantages to_generating a complete

library

from scratch1. The

alternative would have been to create a _matching component

library

for the

NSA celllibrary.

The test _chip consisted of

MUXes,

D

flip-flops,

and an 8-bit adder. The

MUXes compared the RIT nMOS and CMOS transmission gate MUXes

against the NSA MUX called "dsel". A D

flip-flop

with asynchronous resets

from each

library

was used. For overall speed _comparison, two 41-stage

ring

The RITcellsrequired 1/3to 1/2theareaoftheequivalentNSA _cells,andhad

less input capacitance,while

having

the same drive capabilities. Because of_this,

the RIT cells were faster. Due to less than maximal _contacting and

unnecessarilythinpower_{routing in}the NSA cells

(causing

_{unnecessary internal}

resistance),theRITcells were calculatedto consumelesspower.

Anotheradvantage oftheRITceEsis thatthereare severaldrivesizes available

for each component. The

inverter,

for _example, has nine different drive sizes

forthedesignerto choose from. The NSA

library

offers two sizes of

inverter,

and _only one drive size was available for most ofthe cells. After all of these

considerations were taken into _account, it was obvious that a more useful

library

wouldresult

by

developing

it fromscratch.

The test_{chip has}the distinction of

being

the first RIT design tobe processed atMOSIS.

To testthe

functionality

ofthecell

library,

5additionaltestchipswere designed and fabricated

by

Shishir Ghate2. Each component on the test chips has its

own output pad. This was done to allow for more accurate results from the testing. One could have conceivably placed _many more components inside

each test _chip and multiplexed the outputs. Although this would have allowed more components to be tested per _chip, it was determined that the

multiplexing would have been detrimental to the final cause of _obtaining accurateresults.

C. The Commission

of aMorphological

Chip

Set

In April

1990,

Professor Edward

Dougherty

from the Center for

Imaging

Science discussed morphologyandthemorphologic operations of erosions and

dilationswiththe

faculty

inthe Computer

Engineering

Department.

In June

1990,

Computer

Engineering

graduate student Jeff Hanzlik was

selected as principal investigator for the exploration of a prototype

morphologic platform. Itwas decidedtoimplementa 7x7 morphological_array

processor on a printed circuit board that could be inserted into an IBM

PC/AT compatible machine and operate on 512x512 pixel 8-bit gray scale

images4.

In September of

1990,

Computer

Engineering

graduate student Jens

Rodenberg

joined the project.

Initially

_working with simulations of

morphological operations he developed a new architecture

by

November,

wherebythe undefinedpixels _{(represented mathematically}

by

negative

infinity)

were

implicitly

definedvia control

bits,

as opposed to the original architecture

that required explicit negativeinfinities in the data path. The new architecture

also employed enhanced _pipelining,

thereby

increasing

the _efficiency of the

processor3.

An initialgoal wasto fittheprototype onto anATstandard card_{using ACTEL}

gate_arraychips.Thisprovedtobe

impossible,

astheActelgate_arraychipsthat

wereuseddidnotallow ahighenoughlevelofintegration. Itwas also _originally

desired to have the prototype operate in real time.

Again,

due to Actel speed

limitations,

the

technology

prevented the desired performance from

being

In 1991 Computer

Engineering

graduate student Lawrence Rubin joined the

project with the goal of

designing

a single VLSI chip Morphological

Array

Processorthatwouldreplace 23 oftheActelgate arrays fortheprocessor_array

itself1.

Later,

Computer

Engineering

graduate student Chris Insalaco joined the

project to design a smaller more integrated

2-chip

set Controller to replace 5

Actelgate arrays ofthe control

logic,

while also

increasing

performance. Also

Computer

Engineering

graduate student Shishir Gate joined the project to

design the pre and post Arithmetic Logic Units for the MAP _chip set to

III.

Theory

A.

Morphology

Morphological image

processing

refers to the analysis and

processing

of an

image based upon a knowledge of its structure or form with the intent of

modifying

that form or structure. The theoretical basis for morphological

image

processing

dates back to the work of H. Minkowski on spatial set

algebra. Based upon _{this work,} G. Matheron and J. Serra of France and S.

Sternberg

of the U.S. have developed a set-theoretic approach to image

processing5'6. In this _approach,

binary

images are treated as sets in a

background space that can then be actedupon

by

the usual set operations of

union and

intersection,

in conjunction with another image set called a

structuring element. The structuringelement is used to probe or fit the image toextractinformationaboutits shape.

For grayscale images theset operations of union andintersection become the

maximum andtheminimum

functions,

respectively.

The two fundamental morphological operations are dilation and erosion. Dilation of an image yields an image that _{is uniformly larger} than the original

image while erosion of an image yields a _uniformly smaller image.

Building

upon the basic morphological _operations, a large variety of morphological

filters can begenerated for such applications as edge

detection,

_{segmentation,}

/.

EUCLIDEAN MORPHOLOGY

Morphological operations are built upon the set operations union and

intersection

as well as the translationand reflectionoperations. Givenanimage

A inR2

thetranslationofA

by

thepointxin R2

is defined by:

T^A =

{a

_{+x : a e}

A}

wheretheplussignreferstovector addition.

(1)

Considering

the pointx to be avectorin the _plane, T^A. is A translated _along

the vector x. A reflected

image,

B^ in R2 is one that has been rotated 180

around the origin or _{alternatively} one that has been flipped from left to right

and

from

top

to bottom. The first fundamental operation in morphological

analysis is Minkowski addition. Given two images A and B in R2 _, the

Minkowskisumis definedas:

AB =_uTbA = _u

{a

₊

b:aeA}

(2)

beB beB

A Bisconstructed

by

translating

A

by

each element ofBandthen

taking

the

union of all the _resulting translates. The second fundamental morphological

operation is Minkowski subtraction. Given two images A and B in

R2,

Minkowskisubtractionis definedas:

A0B = _nTbA = _n

{a

+

b:aeA}

(3)

beB bB

A B is constructed

by

translating

A

by

_every element of B then the

intersection ofthe_resultingtranslatesistaken.

In morphological _processing, the Minkowski sum is referred to as a

dilation,

D

(A,B)

= _{A B}

(4)

The morphological operation erosion has two different definitions in the

literature. Serra defineserosionasMinkowski_{subtraction6,}denotedas:

E

(A,B)

=_{A 0 B}

(5)

whereas

Sternberg

andMatheron6defineerosionas:

E

(A,B)

=_{A 0}B^ = _nTJl

(6)

beBA

This seconddefinitionoferosion willbe usedforourpurposes asit lendsitself

betterto a digital implementation. Thesecondimage B is generally referredto

as the _structuring element. If B =

BA,

as it usually

does,

then erosion again

becomes equal to Minkowski subtraction. Another form of the Minkowski

subtraction equation is very useful in image _processing, it states that the Minkowski subtraction ofB from A is composedofall elements x in

R2

such

thatBtranslated

by

xisasubset of

A,

whereB^0. This is denotedas:

A B = _{x:T^Ac

A}

(7)

Thisequation can alsobewritten as:

AOB^^iT^cA}

(8)

Analternativedefinitionof erosion canthenbewritten as:

Another form ofthe Minkowskiaddition

(dilation)

is also _veryuseful Itstates

that the Minkowski sum is composed of all elements x in R2

such that BA

translated

by

xisnota subset of

A,

whereB^

0.

Thisis denotedas:

D(A^)

=

{x:TIBA(rA}

(10)

These are the forms ofthe erosionanddilation equations that are usedin the

digital implementation.

Erosion anddilation areoftenperformedin succession onanimage.A dilation

followed

by

an erosionis calleda "closing" operationandis denoted:

C

(AJ3)

= _E

(

D

(AJT),

B*)

= _{(A9BA)0B (1}

1)

An erosion followed

by

adilationis calledan "open" operationandis denoted

by:

O

(AJ3)

=_D

(

E

(A3),

B)

= _(A

BA)

B

(12)

Some of the properties of Minkowski _addition, Minkowski _subtraction,

openingand_closingwill nowbepresented.

A B =_{B A additioniscommutative}

(13)

A B*B A subtractionisnotcommutative

(14)

(AB)C=A(BC)

additionisassociative

(15)

Associative addition allows _structuring elements to be decomposed and

chained to achieve the effect of larger structuring elements from small

(AB)C

=Ac0B

(16)

(A

0

B)c

=Ac _B

(17)

Dilation and erosion are dual _properties, the dilation ofthe background of an

objectisthe sameasthe erosion ofthe_object,and vice versa.

ifAcBthenABcBC

(18)

ifAcBthenA0BcB0C

(19)

Additionand subtractionare both

increasing

operations.

A(TJB)=TX(AB)

(20)

A<8>

(T3)

=

CTA)

0 B =_TX(A

B)

(21)

Additionandsubtractionarebothtranslationinvariant.

O

(A3)

cA

(22)

Open is antiextensive, the open operationtends to decrease the spatial extent

ofanimage.

C

(A3)

₂A

(23)

Closeis _extensive,theclose operationtends toincreasethespatialextent ofan

image.

O (O

(A,B),

B)

= _O

(A,B)

(24)

C (C

(A,B),

B)

= _C

Openand close areidempotent (repeatedapplicationshaveno effect).

if A cFthenO

(A3)

c O

(F,B)

(26)

ifA cFthenC

(A3)

cC

(F,B)

(27)

Openandcloseare

increasing

operations.

2.

DIGITAL MORPHOLOGY

Let F

(j,k)

be a

binary

valued image matrix. A pixel at coordinate

(j,k)

is an

element ofimage F

(j,k)

ifand _{only if it is} a logical one. An image B

(j,k)

is a

subset ofan image A

(j,k)

if for every logical one pixel in B

(j,k)

there is a

logicalonepixelin A (j,k). An image Fc

(j,k)

is the complement ofF

(j,k)

ifall

the pixels in Fc

(j,k)

are the opposite

logically

of those in F (j,k). A reflected

image FA

(j,k)

is formed

by

flipping

theimagematrix F

(j,k)

from left to right

andfrom

top

to bottom. Translation of animage consists of_shiftingtheimage

by

rrows andc columnsfromtheorigin.Thisis denotedas:

G(j,k)

=

TI>c{F(j,k)}

(28)

For the

following

definitions,

assume anNxNimage matrixF

(j,k)

and an

LxL,

where L is _{odd, structuring} element matrix H (j,k). Minkowski addition is

defined,

similarto the Euclidean_case,as:

G

(j,k)

=_U

Tr,c

{F

QJl)}

(29)

The

resulting image

size is MxM where M = _N + L 1. The definition of

dilationisthen:

G(j,k)

=

F(j,k)H(j,k)

(30)

Minkowskisubtractionis similarly definedas:

G(j,k)

=

nTr>c{F(j,k)}

(31)

(r,c)eH

andthedefinition oferosionisthen:

G

(j,k)

=_F

G,k)

0HA

(j,k)

= _n

T,,c

{F

(j,k)}

(32)

(r,c)eH-Another definition of

dilation,

analogous to the alternate definition in the

Euclidean_model, based on the _scanning and

processing

ofH

(j,k)

over F

(j,k)

is:

G

(j,k)

= _U

{F

(m,n)

nH

(j-m+S,

k-n+S)}

(33)

(m,n)

where _max[l,

j-Q]

< m <_minfN,

j+Q]

and _max[l,

k-Q]

< n < min[N,

k+Q]

andS = _{(L+ l)/2and}

Q

= _(L- l)/2.

Thealternate definition forerosionis similarly definedas:

G

Q,k)

= _n

{F

(m,n)

U H

(j-m+S,

k-n+S)}

(34)

(m,n)

where the same limits apply as for dilation. The digital opening and _closing

equations can also be defined analogously to the

corresponding

Euclidean

operatorsas:

O (F

Ji)

=_D

(

E

(F,H),

H)

= _[F

(j,k)

0

HA

C

(F.H)

= _E

(

D

(F,*r), H")

= _\F

(j

,k) HA

(j

*)]

H

(j,k)

(36)

3.GRAY SCALE

MORPHOLOGY

Let F

(j,k)

bea_grayscaleimagequantized to an_arbitrarynumber of_gray

levels,

n, whose pixelvalues can be between zero and 2n

- 1 _or

undefined, (*).

Only

definedpixels_{may be}elements ofthe_grayscaleimage.Anundefinedpixel

may

come about

by

a_varietyofmethods. It may be dueto a sensorproblemorthe

pixel_{may simply be} outofthebounds ofthe_{image. For gray} scaleimages the

union operationis interpreted as the maximum ofthe two inputimages taken

point

by

point. The intersection operation is interpreted as the minimum of

the two images taken point

by

point. The usual maximum and minimum

definitions canbe extendedto include undefinedpixelvalues

by

treating

(*)

as

if it were negative infinity. The max oftwo defined pixels is the highest value

pixel themax of a defined and an undefined pixel is the defined pixel _value,

the max oftwo undefined pixels is (*). The min oftwo defined pixels is the

lowestpixel_value, the min of a defined and an undefinedpixelis

(*),

and the

min of two undefined pixels is (*). The complement Fc

Q,k)

of a _gray scale

image F

(j,k)

is found

by

_{replacing every} pixel _value,

i,

with 2" 1 - i. The

translation, and reflection ofa _gray scale image are defined and denoted the

same as

they

are for a

binary

image. For an NxN image matrix F

(j,k)

and an

LxL,

where L is _{odd, structuring}element matrix H

(jjs),

_gray scale Minkowski

additionis defined as:

G

(j,k)

=_max

[Tv

{F

(j,k)}]

(37)

(r,c)eH

G(j,k)

=

min|Tr>c{FO,k)}]

(38)

(f,c)

eH

Thealternate formofthedilationoperationis definedas:

G

(j,k)

= _{max [F}

(m,n)

+H

(j-m+S,

k-n+S)]

(39)

The alternateform oftheerosionoperationis definedas:

G

(j,k)

=

min \F

(pap)

+H

(j-m+S,

k-n+S)]

(40)

wherethe samelimits asabovefor

binary

images hold. It_{may be}ofinterest to

comparethe above equation withthe

defining

equationforconvolution. Inthe

dilation and erosion equations themaxor minoperations are analogous to the

summations in the convolution equation andthe point

by

point additions are

analogous to the point

by

point multiplication's in the convolution equation.

Similar to _convolution, dilation can be thought of as the _scanning and

processing ofF

(j,k) by

H

(j,k)

rotated

by

180 . The gray scale

opening and

closingoperations are onceagaindefinedas:

O

(F,H)

= _D

(

E

(F,H),

H)

= _[F

(j,k)

HA

(j,k)]

H

(j,k)

(41)

C

(F,H)

=_E

(

D

(F,HA),

HA)

= _\F

G,k)

HA

Q,k)]

0 H

Q,k)

(42)

where now_gray scale erosions and dilations are performed. Because the max

and min operations involved in erosion and dilation can be performed

sequentially, the erosion and dilation operations can be decomposed into a

series ofiterative erosions ordilations toaccomplishthesame effect as alarger

structuring element. Three iterations of a morphological image

processing

operation_using a 3x3 structuringelement accomplishes thesame effect as one

B. Design Rule

Checking

A design rule checker checks that _{the widths, spacings,} and overlaps ofthe

features in a layoutmeet some minimum _rules, the designrules. These design

rules are due to the limitations inthe integrated circuit_{manufacturing} process.

Many

differentmechanisms can contribute todeviations in feature shapes such

as _{electromigration,} mask_{misalignment, overetching,} variations in photoresist

exposure, and the spread ofdiffusion and implant regions around transistors.

The purpose of design rules is to attempt to guarantee _that, under the

accumulated set of process _{variations, the} circuit continues to function as

designed. The Mead and

Conway

design rules are specified in relative terms

usinga scaleable unit,lambda

(X),

instead ofdistances such as microns7.These

designrules are conservative enoughto allow fabricationat a smaller_geometry

by

simply changingthevalueofX.

Using

themostconservative value for each

design _rule, a simple set of _spacing rules is produced. If layout

density

is

important,

then a larger variety ofdesign rules must be considered. There is a

trade-offofincreased design checking time for denser rule sets because more

complicateddesignrulesinvolvemorechecks.

Design rules are constraints imposed on the _geometry oflayouts expressed as

minimum separations andminimum sizes oflayout features. Designchecksare

specified between both drawn layers and derived

layers,

that is layers that are

made _up of combinations of the drawn layers. For example, transistors are

created at the areas where polysilicon and diffusion overlap. The analysis

software canperform the Boolean operations

AND, OR,

and NOT on these

layers to create derived

layers,

such as a transistor layer. The more derived

layers

that are

defined,

the greater the design checking time and _memory

utilization.

Integrated circuit layouts consist ofa collection ofpolygons of various colors

representing

features in different mask levels. Design rules _{generally specify} rules onthe edges ofthe_polygons,insteadof onthepolygons themselves. One

method ofrule _{checking is} to breakpolygons and rectangles down into their

edges and perform rule _checking on the edges. This

initially

increases the

amountofdataobjects as therearemore edgesthanpolygons.

But,

itturnsout that half ofthe edges can be removed from the edges data without loss of information

by

_addinga direction bit to indicatewhich side ofthe edgeis the insidearea. Because almost all layouts are _{orthogonal, usually half}oftheedges

canbe eliminated.

Other methods of design _{checking include} corner-based (or

tile-based)

checkers such as Magic and

pixelmap

(or raster) checkers9.

Pixelmap

checkers

onlywork onManhattan geometry. A small windowis passed over the design and comparedwith a

lookup

table. The window sizeis a function ofthe grid

spacing. For a layout with a small grid spacing, a larger window is required. Because the

lookup

table size _grows, based on the window _size,

pixelmap

checkers have large data requirements that make them impractical for

big

designs. Corner-basedcheckersare alsolimitedto _{Manhattan geometry}andare

most often used as interactive solutions. These algorithms are based on the

premisethata rule need _{only be}checked atthe _{corners, therefore}most design

rules can beverified

by

_{only checking}the corners ofthelayout.

Unfortunately,

specifyingthe rules fora corner-based design checkeris very difficult. We will discuss only edge based checkers for the rest of the _thesis, as that is the

method most

frequentiy

used

by

tools such as the Cadence Dracula II tool

Layout analysis tools work on a "flat" representation ofthe

layout,

with all of

thedesigns

hierarchy

levels removed. The first step ofthe designrule checker

programis toreadinthe layout file and flattenthe

hierarchy by

_expandingthe hierarchical instances. Next

touching

polygons on the same layer are _merged,

and then the polygons are converted to edges. The goal of _merging the

polygons is to remove _{unnecessary internal} edges in the layout. To prevent false spacingrule violations from edges in the same _node, when polygons are

merged,a unique identificationnumber is assigned to them. Thisnumber _may becheckedbefore applying spacingrules checks.

A common set of operations performed

by

design rules checkers on the

flattened layout are

bloating

and shrinking.

Bloating

enlarges and _shrinking

contracts thelayout

by

a uniform distance. To determine iftwo features on a

layer are too close _together, the layout can be bloated

by

halfthe design rule

distanceand re-examined.

Any

_{resulting overlap is} a violation ofthedesignrule

limit. Ifthe _overlappolygonis expanded

by

_slightlymore thanhalfthe design

rule, andANDed withthe originalpolygon_edges, then the edges in errorare

highlighted (see Figure1). Minimum feature sizes can bechecked on alayer

by

shrinking

by

halftheminimum sizeforthelayer. Enclosurechecks of onelayer

around another, such as contact _cuts, canbe calculated as aminimum _spacing betweentheinside layerandthecomplement ofthe_{enclosing layer (see Figure}

2). To check transistor gate _overlap, another type ofexpansion is used. Each

polysilicon edge is expanded in a perpendicular

direction,

then the _{overlap is}

checked (see Figure 3). To prevent erroneous minimum _spacing violations

from

being

detected,

where the polysilicon and diffusion lines run into

transistors, the expandedpolysiliconarea (calculatedabove for overlap) canbe

subtracted from the polysiliconlines before performing the minimum _spacing

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Check

i

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s

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liljli

lIlN;

iillili

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and

Check

Rules that check contact _overlap and transistor _spacing require Boolean

operations to be performed on the input mask layers. It is simpler to first

perform the Boolean operations on the layers to derive the _transistor,

transistor-overlap,

and contact area pseudo-layers. Then the minimum width

and _spacingrules canbeperformed _usingthesenew pseudo-layers. The design

rule checkis therefore a two _{step operation,} one _step to derive the

pseudo-layers,

andone_stepto checkthewidth andspacings of allthelayers.

A design rule language is used to describe the derived pseudo-layers and the

design rule specificationsfor the process. Three typesofdesign checks canbe

defined: width_{checks, spacingchecks,}and enclosure checks. Width checksare

defined

by identifying

the

layer,

theminimumwidth andthe rulename; _spacing

checks are defined

by

identifying

the two

layers,

the _spacing

distance,

and the

rulename; enclosure checks aredefined

by

_specifying theinternal and external

layers,

the_overlap,andtherulename.Whenthedesignrule checkeris

invoked,

the definition file for theprocessis read

in,

and the derived pseudo-layers are

created. Onthesecondpassthedesignrulesare checked.

The output error edges can be reported as a new error layer that can be

overlaid on the original design layout. Ifa separate error cell is reported for

each type ofdesign rule _error, then the user can view one type of error at a

time,

such asmetal-to-metalspacing.

Circuit extraction consists of

finding

the _transistors, the nets between the

transistors, and the transistor areas and perimeters to calculate capacitance

estimates and transistor size. The outputis a list of_transistors, their size and

types, a netlist with the connections between their _gates, sources and

drains,

and alistofcapacitorsfromthenetstogroundorbetweennets.Theestimated

accurate circuit simulations. The netlist generated can be compared with the

circuit schematicto_{verify logic} and schematicare equivalent.

In MOS circuits, transistors are created

by

_crossing polysilicon and diffusion

layers. Different typesoftransistors aredetected

by

thepresence orabsence of

implants and wells. The definitions of the pseudo-layers that comprise the

different transistor types for a fabrication process are added to a

technology

file,

similarto the design rule checker

technology

file. Once each transistoris

uniquely identifiedand thenodes are _numbered, the connections between the

nodes are examined. Connections are preserved over continuous runs on a

layer and through contacts _connecting two layers. Incorrect transistor ratios

and malformed transistors with

floating

nodes or shorts between power and

ground can be identified with a simple electrical rules check. Transistor drive

size is calculated

by determining

thewidth and length ofthe transistors. For

rectangular _transistors, the width is the one half the perimeter with the

diffusion edge, and the length is one half the perimeter with the polysilicon

edge.

Parameter extraction determines the electrical parameters from the layout for

use in refiningthe circuit simulation timing. Thetwo categories ofcapacitance

that can be calculated

during

extraction are area and perimeter capacitance to

substrate, and the capacitance between parallel wires or nodes. Each wiring

layer and transistor type has a differentcapacitance

factor,

whichis a function

ofthe fabrication process. These factors are added to a

technology

definition

file for the process, similar to the design rule checker

technology

file.

During

extraction, theareas andperimeter foreachlayerare calculated_separatelythen

multiplied

by

the appropriate scale

factor,

and the result is totaled to get a

Wiring

resistance canbe calculated for

long

parallel lines as the length ofthe

parallel

lines,

divided

by

the _{distance between them, times} the resistance scale factor for the layer. Transistor resistance is proportional to the length over

width ratio (the inverse ofthe

Z-ratio)

ofthe_{transistor, times} the scale factor fortheprocess.

Generally,

atthetimeofthisproject,mostcircuit extractorsdo

not calculate_wiringresistance for back annotating intothe circuitdesign dueto thelargenetworkofresistors thatwouldresult9.

IV.

Materials

andApparatus

A, Mentorand

Cadence Tools

The additional standard cells for the RIT CMOS standard cell

library

and the

morphological _array controller _chip set were designed on HP/Apollo

workstations _running theAegis _operating system.

The

RIT CMOS standard

cell

library

has already been integratedwithversion 7.0oftheMentor Graphics toolsuite as apartof

Larry

Rubin'sthesis1.The Mentor Graphics development tool suite consists of the Neted schematic capture _tool, the Quicksim logic

simulator, the Accusim SPICE circuit _{simulator, the} Cellgraph cell automatic place and route tool, and the Chipgraph _{hand layout editing} tool. In addition the Cadence Dracula II design rule checker

(DRC),

electrical rule checker

(ERC),

layoutversus schematic

(LVS),

and layoutparameter extraction

(LPE)

tool suite will be utilized. The Mentor Graphics tool suite is licensed and

available on all ofthe HP/Apollo workstations in the lab. The Cadence tool

suiteis only licensedtorun on twoworkstations withinthelab.

When a top-down _{design methodology is used, the} design process is divided

circuit

design,

and physical design. These design representations are used to

describe different levels ofabstraction ofthe system. The design automation

process consists of a series of iterations _of, and conversions

between,

these

different representations of a system.

Mamtaining

_equivalency across the

different design representations is an important issue for design automation

tools.

The design specification stage is the manual process of_specifying the system

requirements. The behavior of the _system, as a function of the inputs and

outputs,is described

during

functional design. Logicand circuit design describe

thelogicalor schematic structure ofthe systemtomatchthe functionaldesign.

Physical design involves _converting the circuit structure into the format

requiredtomanufacturethephysicaldevice.

Each of the design phases _{may be} composed of _{synthesis, analysis,} and

verification steps and therefore the design automation tools utilized

during

these steps can be categorized as _{synthesis, analysis,} or verification and

validation tools9. Synthesis tools generate a new representation of a

design,

such as the Mentor Graphics Cellgraph automatic place and route tool.

Analysis tools evaluate the _consistency or correctness of a design

representation. The Cadence designrule checker

(DRC)

is an example of such

a_{tool, it} checks thephysicallayout for geometric ruleviolations. The Cadence

electrical rule checker

(ERC)

is another _example, it checks that the circuit

extractedfrom the layout does not have anyelectrical errors such as shorts or

floating

nodes. Verification tools provide a formal method for

demonstrating

the equivalence of two design representations. The Cadence layout versus

schematic

(LVS)

tool verifies that the circuit extracted from the layout is

equivalent to the circuit design representation. Validation demonstrates the

equivalence oftwo _{designs using}alimitedsetoftest cases. Itis a less rigorous

In the functional design stage the functional behavior of the design is represented. _{This may} consist of

timing

_charts, block

diagrams,

or behavioral models. Mentor Graphicssupportsmodelswrittenin

C,

Pascal,

FORTRAN,

or

VHDL. Behavioralsimulation with a series oftest vectors is used for analysis.

Mentor Graphics Quicksim was used for behavioral simulation. Logic design

involves

implementing

the functional design at the gate logic level using a

schematic diagram. The logic design is validated against the functional design

by

comparing

the results of the behavioral simulation with the logical

simulation. Mentor Graphics Neted was used for schematic capture and

Quicksimwasonce again usedfor logic _{simulation,using} aunitgate delay. The

circuitdesignphaseinvolves

implementing

thelogic design behaviorwithbasic circuit elements such as transistors and capacitors.

During

the circuit design

phase, transistors are sized to achieve drive and

timing

requirements and

subsequently the _{logic design may} undergo some minor changes as the gates are sizedtomatchtheload. Netedwas usedtomake changesinthe schematic and the Mentor Graphics Accusim SPICE simulator was used for

timing

analysis.

During

thephysicaldesign_phase,thecircuitdesignwas convertedinto the geometric layout used in the fabrication process. The Mentor Graphics Cellgraph toolwas used for automatic synthesis (placement and routing). To hand layout the standard cells and correct unrouted and _poorly routed lines resulting from a Cellgraph automatic place and _route, the _{designer may} use

Chipgraphto editthephysicallayout. Cadence

DRC, ERC,

andLVStoolswere used for analysis and verification. The layout is verified to conform to the designrules

by

the Cadence Dracula II designrule checker (DRC). The circuit

extracted from the layout is checked for electrical errors such as shorts and

floating

nodes_{using its}electricalrulechecker

(ERC),

and verifiedto_mapto the

design,

and re-simulate the circuit for greater _{accuracy using Cadence Dracula}

IIlayoutparameter extraction (LPE).

Some of these design rule _{checking functions have recentiy been} added

by

Mentor Graphics intheirREMEDI and Checkmateprograms. The Checkmate

tool has been installed and _setup

by

Chuck

Carline,

following

the completion

ofthelayout designwork on this thesis. Checkmate can perform

DRC,

ERC,

LVS,

and LPE functions similar to the Cadence toolsuite but it also has the

same limitation of_requiring users to exit from Mentor Graphics Chipgraph

tool to run the checkers12. The advantage ofthe Checkmate installation over

the Cadence installation is that the software licenses are not node locked to

onlytwo_{workstations,}so

they

canrun on _anyoftheHP

/Apollo

workstations

in the lab. At this

time,

Checkmate LPE has not yetbeen configured for the

MOSIS 2.0 pm N-well CMOS process. The REMEDI tool is a design rule

checker that Jeff Correll has integrated with the Chipgraph tools menus

through a set ofmacrosinvoked atChipgraph startup13. Because REMEDI is

invokedfromwithintheChipgraphtool_menus, itprovidesamoreconvenient

firstpass designrule checkthan theCadence or _{Checkmate DRC tools,}which

must be invoked after _exiting out from Chipgraph. On the other

hand,

REMEDI should _{only be} used as a first pass

DRC,

because it does not use

layoutnode data to _skip same node checks or allow the definition of

pseudo-layers. Therefore Cadence DRC orCheckmate shouldstill be run on the final

layout. When used in conjunction with Cadence or Checkmate

DRC,

REMEDI can reduce the number ofinvocations of Cadence or Checkmate

DRC,

andtherefore the totallayout design time.

A

series of scripts developed

by

Shishir Ghate and

Larry

Rubin,

designed to

work in conjunction with the Mentor Graphics MCIF _package, are used to

convert the final Chipgraph layout data into the Caltech Intermediate Form

B.

Tektronix

Logic Verifier

The

Tektronix

Logic Verifier 500

(LV500)

can be used to _efficiendy test

complicated circuitdesigns. Thesystemthatis in currentoperation atRITcan

handle up to 64 different bi-directional signals. It can be driven

by

_up to four

independent

clocks (which can be distributed in anymanner). The LV500 is

primarily

used forthe

testing

ofdigital circuits and has been enhanced at RIT

by

the addition ofa breadboard. With the breadboard an IC can be

direcdy

interfaced

to the LV500. Another useful feature of the LV500 is its

compatibility with the Mentor Graphics tools in RIT's VLSI Design

Laboratory.

Specifically

the application TekWAVES can be used to translate

Mentor Graphics test vector (event

driven)

format into the LV500's state

driven format.

Essentially

TekWAVES samples the event state changes from

the HP/Apollo state file and creates an output file that matches the state

format and resolution ofthe LV500.

Thus,

one _{may design} and test an IC

using Mentor Graphics tools, fabricate that IC with the aid of RIT's

Microelectronics facilities or

MOSIS,

and then test the circuit _using the same

testvectorsthatwererunonthe HP/Apolloworkstations.

V. MethodofProcedure

The overall procedure ofthis thesisfollowedthese steps:

A. Write the Cadence Dracula II layoutverification systems

DRC, ERC, LVS,

andLPE

technology

(".com")

files fortheMOSIS SCN 2.0 pm N-wellCMOS

B. Create additional

library

components and cells for the RIT CMOS standard

cell

library,

as needed to complete the Morphological

Array

Processor

Controller

chip

set.

C.

Layout

test_{chip 5} and6to test the

functionality

ofthe RIT CMOS standard

cell

library

_MUXesandD

flip-flop

cells.

D. Design a _{Morphological}

Array

_{Processor Controller chip} set_usingthe RIT

CMOS standard celllibrary.

1.The

functional

designarchitecture oftheMAP Controllerchip.

2. Perform the

top

level

design

ofthe MAP _{Controller chip} set _{architecture,}

andpartitionthe_chip set.

3. Performthelogic designoftheControllerand

Memory

Controller.

4. Simulatethelogic designoftheControllerand

Memory

Controller.

5. PerformthecircuitdesignoftheControllerand

Memory

Controller.

6. SimulatethecircuitdesignoftheControllerand

Memory

Controller.

7. LayouttheControllerand

Memory

Controller.

8. Performthe designrule_checking

(DRC),

electricalrule _checking

(ERC),

and

layoutversus schematic

(LVS)

_checkingonthelayouts.

A.

Cadence

Dracula

II

Layout

Verification

Tools

Setup

Inthe designrule

theory

_section,mentionwasmadeoftheneedfora separate

technology

definition

file for each fabrication process anddesign rule checker;

DRC, ERC, LVS,

and LPE. Also mentioned in the

theory

section, was the

need to define inthe

technology

files the input layers and pseudo layers used

by

therules_checkers, andthe specificdesignrules andparametervalues forthe

fabrication

process used. The MOSIS scaleable N-well CMOS

(SCN)

process

denserules set revision6was chosentoallowformore compacteddesigns.

The first step involved with

defining

the DRC

technology

file for the MOSIS

SCNprocess (see Appendix

A,

DRC.COM

File)

was todefinetheinput

layers,

the connection

layers,

and the _{connectivity relationship between} the connect

layers utilized

by

the process. The connect layer definitions are utilized for

samenode checking. The *INPUT-LAYERto*ENDblockcontains theinput

and connectionlayer definitions. The CONNECT x _{y BY}z statements define

the two layersto be connected,x and_y, andthe connection

layer,

z. The next

step involved

defining

a minimum set of pseudo layers to define n and _p

transistorgates as wellasother

temporary

layersused to perform various rules

checks suchas contactcut enclosure.Aminimum number oflayers is

desirable,

as each additional pseudo layer involves time and

memory

overhead. The

AND, OR, XOR,

and NOT statements are used to define the pseudo layers.

The firsttwo _{layers specify}theinputlayers

(possibly

pseudo layers

themselves)

to perform the Boolean action _upon, and the third layer the pseudo layer

created.Thefinal step involved

defining

a setofrules checks_utilizingtheinput

layers and pseudo layers to check for each ofthe dense rule set violations. A

separate output error layer is specified to be created for each rule check

violation souserswillbeaware ofthedesignrule violated. WIDTH statements

define minimum width _checks, EXT statements define minimum

checks, and ENC statements define enclosure checks. In the definitions the

OUTPUT

statement defines the output error cell layer. In most cases a single

check is _sufficient, but for those rules with multiple possible error

combinations, such as rule 4.2 (pplus or nplus _overlap of _active), it was

necessary

to define an "a" and "b" set of rules checks to cover both

possibilities. All of the rules checks were then verified _using a test "chip"

consisting

of the specific examples from the MOSIS rev6 dense rule set

documentation.

In some cases additional pseudo layers were defined to

minimize false errors and improve error

detection,

_particularly the SELECT

tests. _{In specifying} the error _checks, it is preferable to err on the side of

generatingsomefalseerrors ratherthan_missinganactualerror.Users canthen

usetheirbest judgmenttoevaluatethose errors flaggedto determine ifan error

isa falseone.

The ERC and LVS

technology

file definitions (see Appendix

B,

LVS.COM

File)

were ableto borrowtheinput layer andpseudo layer definitions fromthe

DRC definition

file,

after removal ofthose pseudolayers created _specificallyto

check for DRC rule violations that are _{unnecessary for definition} of the

transistorswithin thelayout. Thenext_{step for both}rule checkers wasto define

the transistor nodes _using the ELEMENT statement. For ERC it was also

desirable to define the standard composite gate _types, such as NAND and

NOR _gates, so output errorreports would utilize thatinformationto _simplify

and _clarify output error _reports, rather than _reporting all output in terms of

individualtransistorsalone.

The LPE

technology

file definition (see Appendix

C,

LPE.COM

File)

was

similarto thatfor

LVS,

butalsoinvolveda _steptodefinethepseudolayersthat

would be utilized for calculating parasitic capacitances and

diodes,

such as

p

diffusion to

p

substrate capacitance. The PARASITIC CAP statement

defined

these capacitancetypes _usingtheATTRIBUTE CAP statement,basedon data

supplied

by

MOSIS. It was also specified that the capacitances should be

"smashed"

togetherintoa single valueforeach node. As the tooldidthisafter

calculating

eachcapacitance value _separately,this turnedout to be a significant

limitation

of the _tool, as _{only 500,000} capacitance values could be evaluated

priorto"smashing". This limitedtheusefulnessofLPEtosmallerlayoutsonly.

B.

Additional Standard Cells

In the course of _completing the design for the MAP controller _chip set it

became necessary to design and layout additional RIT CMOS standard cell

library

components and cells. InparticularadditionalD flip-flops withboth

Q

and

Q

bar _{outputs, and-or-inverts, or-and-inverts,}

CMUXes,

and MOSIS 64

and 84pin pad rings were created (see Figure 5 through Figure 9). Each cell

design was

DRC, ERC,

and LVS tested before addition to the RIT CMOS

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C. Test Chips

5and6

As a part of his thesis, Shishir Ghate was asked to _verify the RIT CMOS

standard cell

library

designs and to calculate the internalnode capacitances of

the designs for use in back annotating the standard cell circuit schematics.

Shishir performed the schematic design in Neted for the six test _{chips, along}

with the layout and verification of four of the test chips2. The layout and

verification ofthe finaltwo test chipswas performed

by

the author. Test chip

five contains size A through C two-input

MUXes,

size A and B three-input

MUXes,

sizeA four-input

MUX,

size AandB five-input

MUXes,

anda_variety

of D flip-flops (see Figure 10). Test chip six contains a _variety of _nMOS,

pMOS,andCMOStransfer_gates,individual

p

gate andn gate _transistors,and a

variety ofinverters (see Figure 11). Each chip was layed out and verified _using

DRC,

ERC,

and LVS. Test chip four had an LVS error that the author was

unable to locate prior to shipment of the test _{chip layouts} to MOSIS for

fabrication. This test _chip contained some MUXes and D flip-flops whose

design was later changed for other _reasons, so the loss was not appreciable.

Thereason forthe LVSerrors turned outto bea resultofthe automaticplace

and route tool. Cellstation did not always complete the placement of _every

interconnectionline

during

cell routing. The author _{only became} aware ofthis

problemlater

during

cellplaceandrouteforthecontroller_{chip set,}asthe tools

error message to this effect is difficult to find in the cell place and route

transcript.

Luckily

the author was then aware of this issue and was able to

verifythecorrect automaticplace and routefor bothcontroller chips.

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D. Morphological

Array

ProcessorController Design

/.

The Functional

_{Design Architecture of}theMAP Controller

Chip

The implementation ofamorphological operation is accomplished

by

_moving

awindow composed of_patterning elements over an image. The target image

pixelis the pixel underthe center window element. Operations are performed

onallpixelswith awindowvalue above_them,withthe_resultingvalue_replacing

the originaltargetpixelvalue.

When the construction of a Morphological Image Processor prototype was

proposed,itwasdecidedthat theimagewouldbe 512x512pixels _usingan 8-bit

gray scale pixel_{representation,} with an extra bit used to represent undefined

pixels (shown as * in the Morphological

Theory

section). These undefined

pixelscanbe implementedandtreatedasif

they

were negative

infinity (-00)

and

will be represented as such in future references. The

meaning

of negative

infinity

was discussed in the Morphological

Theory

section and since it was

possible to use the extrabit to also represent negative pixel _values,

they

were

included incase a use is ever found forthem. Table 1 shows the

binary

pixel

values and their _{corresponding decimal} values. _Negative values use the two's

complement _{representation,} with negative

infinity

_using the value that would

normallyrepresent-512. Sincemostimage capture and

processing

systemscan

only dealwith 8-bit grayscale images andhaveno concept of negative

infinity

and negative pixel_{values, the} 9-bit gray scale system will be referred to as an

patterning

elements, also _using the extended 8-bit _gray scale pixel

representation.

Binary

Decimal 0 0000 0000 0

0 0000 0001 1

0 0000 0010 2

; I

01111 1101 509

01111 1110 510

01111 1111 511

1 0000 0000 -00

1 0000 0001 -511

1 0000 0010 -510

:

i mi noi -3

i mi mo -2

i mi mi -1

Table 1

Binary

PixelValues andTheir Decimal Equivalents

While _choosing an architecture for the Morphological Image Processor

prototype, therewere a fewgoals thatweredesirable to achieve. One ofthese

goals was to allow the processor to operate at areal-time rate (60 images per

second) using the same 512x512 pixel extended 8-bit gray scale images and a

7x7window.

Implementing

the_{design using}aVLSI circuitis currentlythebest

way to achieve the real-time _rate, so a regular structure was desirable to

facilitate aVLSI layout. Another goalwas a simple controlsection to facilitate

expansiontolargerwindow sizes andlarger images.

Also,

the processor should

be designed such thatit is easy to pipeline withidenticalprocessors and allow

theinputs and outputs to be connected to real-time sources and

destinations,

possiblywith some

buffering

to make the system compatible with interleaved

Forthe Morphological Image Processor_prototype,a 512x512 imageand a 7x7

windowwere _used,so all examples and explanations will use these sizes,unless

otherwise noted. All ofthe concepts discussed in this section will work with

any size image and window as

long

as appropriate adjustments are made. All

indexvalueswillstartat0 and end atthe oneless than themaximum_value, for

example, the

top

left ofa 512x512 image will be referred to as

X00

and the

bottom right ofthat image will be referred to as

X511>511,

with the first index

value

referring

tothe rowandthesecond oneto thecolumn.

As

previously

discussed intheMorphological

Theory

section forequations

(39)