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Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler

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Figure

Figure 2.1: High level representation of the Hierarchical Temporal Memory. All the regionsare hierarchically stacked with the lowest level regions exposed directly to the informationfrom the input domain
Figure 2.3: Phase 1: The Overlap phase sets the overlap value to zero for each new columnand counts the number of proximal synapses that are active and connected
Figure 2.4: Phase 2: The inhibition phase obtains the desired column activity for all theneighboring columns in the region
Figure 2.5:Phase 3: The Learning phase checks if a column is a winner.If it is awinning column, all the permanence values of the active proximal synapses are incrementedby the Pinc constant value
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