Dynamic input match correction in R.F. low noise amplifiers

Rochester Institute of Technology

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Thesis/Dissertation Collections

2004

Dynamic input match correction in R.F. low noise

amplifiers

Tejasvi Das

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Recommended Citation

DYNAMIC INPUT MATCH CORRECTION IN

R.F. Low NOISE AMPLIFIERS

by

ApPROVED By:

TEJASVI DAS

A THESIS SUBMITTED

IN

PARTIAL FULFILLMENT

OFTHE

REQUIREMENTS FOR THE DEGREE OF

MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

PROFESSOR

P.

R.

Mukund

(THESIS ADVISOR)

PROFESSOR

James E. Moon

(THESIS COMMITTEE MEMBER)

PROFESSOR

Syed Saifullslam

(THESIS COMMITTEE MEMBER)

PROFESSOR

Name Illegible

(DEPARTMENT HEAD)

DEPARTMENT OF ELECTRICAL ENGINEERING

KATE GLEASON COLLEGE OF ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

ROCHESTER, NEW YORK

THESIS RELEASE PERMISSION

DEPARTMENT OF ELECTRICAL ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

ROCHESTER, NEW YORK.

TITLE OF THESIS:

DYNAMIC INpUT MATCH CORRECTION IN R.F. Low

NOISE AMPLIFIERS

I, Tejasvi Das, hereby grant permission to Wallace Memorial Library of the Rochester

Institute of Technology to reproduce my thesis in whole or in part for

educational/research purposes. Any reproduction will not be for commercial use or profit.

To

my

parents

-forgivingmethefreedomtomak[e

ACKNOWLEDGEMENTS

IcametoR.I.Tinthefallof

2002,

excitedtolearncircuit

design,

eagertoexperiencelife

-and_{mildly put,} these two yearshave been remarkable. In _myadvisor I have found an

extraordinary

person a man who has become my

'teacher'

in the true sense of the

word. In _{my lab} I have found a place which epitomizes

honesty

and

integrity

-and

people whohaveenriched_my

life,

_{professionally}and personally.

I would be remiss if I claim this as "my"

work. Anand Gopalan has been a fellow

traveler on this

journey;

Dr. P.R. Mukund and Clyde Washburn are the reasons this

workis_seeingthelight-of-the-day.

This thesis is a culmination of _my M.S degree and two

years'

work at the

RF/Analog/Mixed-Signal

laboratory

(RAMLAB). To the people who have been an

integralpartof

it,

Iexpress_mygratitude:

DR. S. ISLAM _{for consenting} to be on _{my thesis committee,} for your valuable

comments.

DR. J.E. MOON _{for consenting} to be on _{my thesis committee;} for your rigorous

appraisal of _{my thesis;} for your scrupulousness and _sincerity

towardsstudents.

GHANSHYAM for the innumerable illustrations you'vehelped with; for patiently

enduringthoseperiodicboutsofnear-insanity.

ANAND Ithasbeenfun

-the

debates,

the arguments, themidnightflashesof

gnosis Ourpaths_may

diverge,

butthese timeswillbecherished.

CLYDE WASHBURN foryour patient _{explanations,}brilliantideasand advice. This work

is strewn with innumerable imprints of yours. It has been a

privilegetoworkwithyou.

DR. P.R. MUKUND I have learnt and continue to learn much from you. For your

integrity

and

honesty;

for

inspiring

me towards _my potential; I

could_{have possibly learnt}circuitdesigninother placestoo, butitis

for those other things

-things much more valuable, things that I

could nothave found elsewhere, things thatcannot

be,

need not

be,

explained withwords, thatIamindebtedfor.

It iswith

honor,

thatIcall you_myteacher.

Allwhohaveaccomplishedgreatthingshave hada greataim,have fixedtheirgazeon a goalwhich was

high, one which sometimes seemedimpossible.

-OrisonSwett Marden

Abstract

An R.F.circuitthatrecognizesits

faults,

andthencorrects itsperformance inreal

time has been the holy-grail of RFIC design. This work _presents, for the _{first time,} a

complete architecture and successful implementation of such a circuit. It is the _{first step}

towards the grand vision of

fault-free,

package

independent,

integrated R.F. Front End

circuitry.

The performance of R.F. _{front-end circuitry} can _{degrade significantly due} to

processfaults and parasitic packageinductances atits input. These inductances havewide

tolerances and are difficult to co-design for. A novel methodology, which overcomes

current obstacles _plaguing such an _objective, is proposed wherein the affected

performance metric ofthe circuit is quantified, and the appropriate design parameter is

modified in _real-time, thus _enabling self-correction. This proof of concept is

demonstrated

by designing

a cascode LNA and the complete self-correction circuit in

IBM0.25 urnCMOS RFprocess.

The self-correction_circuitry ascertains theinputmatch

frequency

ofthecircuit

by

measuring its performance and determines the

frequency

interval

by

which itneeds to be

shifted to restore it to the desired value. It then feeds back a digital word to the LNA

which _adaptively corrects its input-match. It offers the additional

flexibility

of _using

different packages forthe front-end since it renders the_{circuitry independent} of package

parasitics,

by

re-calibrating the input match on-the-fly. The circuitry presented in this

work offers the advantages of low power, robustness, absence of DSP cores or

processors, reduction in design cycle times, guaranteed optimal performance under

Table

of

Contents

Acknowledgements

iii

Abstract

iv

Table

of

Contents

v

List

of

Figures

viii

List

of tables x

Chapter 1

.

Introduction

1

1.1

R.F. Integrated Circuits

1

1.1.1 The

System-On-Chip

approach 2

1.1.2 System-ln-Package

(SiP)

implementations 2

1.2 Chip-Package

co-design 3

1.3 Testing

and

Reliability

5

1.4

Necessity

for this work 7

1.5 Preface

to this work 9

1.5.1 PackageIndependence 9

1.5.2 Fault Correction 9

Chapter

2.

Architecture

12

2.1

Why

feedbackwill not work 1 2

Z2

The 'Locked

loop'

concept 1 3

2.3

Sensing

the

Input Match

15

2.4

The

novel'two-tonal'approach 1 7

2.5

Signal

Processing

20

2.6 The

'Tapped

coil'

22

2.7

Self-correction

algorithm 24

2.8

Merits

of this architecture 27

Chapter 3.

Circuit Implementation

29

3.1

Single-ended

1.9

GHz LNA

with

Sensing

resistor 30

3. 1. 1 LNA Design 30

3. 1.2 Tapped Gate Coil 33

3.2

The Sensor

chain

36

3.2.1 Source Follower 36

3.2.2 Amplifier 36

3.2.3 Peak Detector 38

3^4

Timing

42

3.5

Limitations

49

3J>

Implementation Summary

50

Chapter

4.

Simulation

results

52

4J_

Circuit

Response

53

4.2

The

self-correction process 56

4.2. 1Additionofparasiticinductance 56

4.2.2Reduction of

CGS

₆₀

4.3

Robustness

62

4.4

Layout

65

Chapter

5.

Conclusions

68

5J Summary

69

5.1

Future Work

71

List

of

Figures

Chapter

1

1.1 The

System-On-Chip

(SoC)

approach 2

1.2 The integrated System-ln-Package

(SiP)

approach 3

1.3 Package Parasitics 4

Chapter

2

2.1 Theself-correction _methodology 13

2.2 Potential placementsforthe _sensingresistor 16

2.3 The'two-tonal'

approach 18

2.4

Sensing

theinput match _using resistor

Rs

22

2.5 Circuit Architecture forcorrectionof LNA inputmatch

frequency

25

Chapter 3

3.1 Cascode LNAwith tappedgate inductor 31

3.2 Layoutofgatecoil 33

3.3 Pi-model forthegatecoil 34

3.4 Thesourcefollowerand amplifier 36

3.5 Half-wave

inverting

diodePeak Detector 38

3.6 Folded-cascode op-amp 40

3.7 Generationof

"Continue"

signal ₄₀

3.9 Thepulsesforthefourcapacitor outputsof P.D. 44

3.10 'Discharge'

for peakdetector 44

3.11 The2-bitcounter usedto controlthe taps. 45

3.12 Decode logicto turn ontaps in each cycle 46

3.13 Selectionoftaps ineach cycle 47

3.14

Turning

on the ideal

tap

_permanently 47

Chapter

4

4.1 Spectral response ofsensorchain 53

4.2 Thetransientresponse of the sensor chain 54

4.3 Charge leakage is negligible in capacitors 55

4.4 Transfercharacteristic of thesensor chain 55

4.5 Outputvoltages of various stages over entire

correction process.

57

4.6

Sn

curvesbeforeand after correction 59

4.7 Outputvoltages of various stages when

CGs

is

reduced

by

15%.

61

4.8 Sn beforeandafter correction when

CGs

ofthe input transistorisreduced

by

1 5%.

62

4.9 Spectral Response ofSensor Chainovercorners 63

4.10 Transferfunction Sensor Chain over corners 64

4.11

Sn

curves beforeand after correctionforthe

weakestcorner

65

List

of

Tables

3.1 Thetappedcoil values and_{corresponding}

Sn

frequency

34

3.2 The

timing

logicprocesssummarized 48

4.1 Outputof Sensor Chain for alltaps of

Lg

54

Chapter

1.

INTRODUCTION

1.1 RF Integrated Circuits

-1.1 .1 The

System-On-Chip

(SoC)

approach -1.1.2Sjstem-In-Package

(SiP)

implementation 1.2 Chip-package Co-design

1.3

Testing

and

Reliability

1.4

Necessity

forthiswork

1.5 Prefaceto thiswork

-1.5.1 Package independence

-1.5.2Fault Correction

-1.5.3 Organisation

1.1

RF Integrated Circuits

The drive towards miniaturization within the CMOS semiconductor

technology

has led to an unprecedented reduction in transistor feature size with gate oxide

thicknesses afew atoms wide.A significant factor in the success oftheMOS transistoris

the fact that it has been scaled to

increasingly

smaller

dimensions,

improving

performance while

decreasing

power consumption. CMOS integrated circuits have

become ubiquitous in today's electronics

industry,

_offering the advantages of low cost,

small size, high yield and reliability. This rapid_shrinking of channel lengths hasenabled

MOS transistors towork at higher

frequencies,

breaking

theGHz barrier.

Along

with the

increasing

demand forwireless and other formsofhigh-speedcommunication inthepast

few years, these factors have fuelled the development of a wide range ofRFintegrated

7.7.7 The System-

On-Chip

approach

The persistent demands on miniaturization have resulted in escalating levels of

integration. In the circuit board architecture, inter-connection and inter-communication

between the different domains are responsible _{for majority} ofthe real-estate overheads.

The next logical step, enabled

by

rapid strides _{in technology,} was the amalgamation of

analog,

digital, RF,

and mixed-signal _circuitry onto a single _{chip, using} the same

fabrication process. This has resulted in the advent of several

highly

integrated Radio [image:14.525.58.517.281.441.2]

Frequency System-On-Chip

implementations

[1,2, 3],

depictedin Figure 1.1.

Figure 1.1 The

System-On-Chip (SoC)

approach

7.7.2 System-In-Package

(SiP)

implementations

Each of these domains

-digital,

analog, and RF _circuitry pose

different,

and

sometimes _{conflicting demands} on the fabrication process. RF circuitry, for example,

requires

high-quality

_on-chippassives [4]. This inturn necessitates a_{thick, low} resistance

top

metal layerspecialized for

inductors,

and a

high-resistivity

substrate.

Analog

circuits

dominantfactor for digitalcircuits. These incompatible demands amongthe_circuitryofa

single systemhas led to the development of an alternate means ofintegration: while the

circuits are fabricated on different

dies,

which enables the use of different fabrication

processes,

they

are integratedontothesame_package,

leading

toSystem-In-Package

(SiP)

implementations

[5,6,7]

(3-Dstacking,

Multi-chip

modules, etc.,Figure 1.2).

RF Modules Horizontal Floor

[image:15.525.50.463.166.352.2]

Planning

Figure 1.2 ThenstejiratedSysLem-In-Package

(SiP)

approach

In either approach, the complex interaction of signals across _{the analog,} digital

and RF domains and the chip-package interactionsplace a huge burden on the_packaging

technology. The package exerts significant influence on the system _performance, and

consequently, its accurate characterization is a _{necessity for} the success of such RFIC

implementations.

1.2

Chip-Package

co-design

The rapid increase in circuit _operating speeds, I/O pin count and

functionality,

challenges on the _encompassing package.

Furthermore,

at radio

frequencies,

package

parasitics are nolongernegligible [8]:

BondWire

Lead Frame

(a)

Bond Wire Inductance

p j MutualInductanceandCapacitance

(b)

Figure 1.3

(a)

Interconnection of _chip and package through bond-wires,

(b)

parasitics associated withthechip-packageinterface.

Inductances ofthe order ofatenth of a_nano-henry and capacitances ofthe order

of atenthofa pico-faradcanhave ahuge influence on chip-performance.

Package bond-wires or solderbumps (Figure 1.3

(a))

are_generally ofthe orderof

afew nano-henry.

Other package associated parasitics that _{influence chip} performance include

In _addition, Electro-Static Discharge devices

(ESD)

present non-negligible

parasitic inductancesand _{capacitances,}and

they

mustbe accounted for

during

the

designprocess [17].

Traditionally,

circuit design and _{its packaging have been} conducted

by

different

groups,

leading

tosub-optimal resultsfroman overallsystem performanceperspective. In

addition, due to the high

frequency

complex inter-module

interactions,

'Package

aware'

design for RF transceivershas become a necessity.

Consequently,

the RFIC

industry

has

accepted a paradigm shift to chip-package _co-design, whichinvolves concurrent design

ofboth chip and package

[9, 10],

where allthe_packagingeffects are accounted for

during

thecircuit design process. Itmust be noted,

however,

thatmost of these parasitics have

very high tolerance

limits,

and this makes it almost impossible to _accurately model or

predict them.

Therefore,

the performance ofRF circuits cannot be accurately predicted

during

design or simulation.

1.3 Testing

and

Reliability

RFcircuits are prone to unique _reliability

issues,

such as _{on-chip inductor}

faults,

ground inductance

loops,

etc. In today's era of

integration,

the RF core exists as a sub

system _{among many heterogeneous} modules, and complexinter-module interactions(for

example, the digital _circuitry can inject switching noise, which can be _severely

detrimental to the RF core _performance) make

testing

an even more critical issue. In

addition, process faults and variations are _only part of the list of probable causes of

variations and result in severe performance degradation. _{The quality factor} of_on-chip

passives is _abysmally low and unpredictable (30%): this can lead to soft-faults in the

circuits. To compound this

issue,

access to the RF core in such a complex system _may

almost prove impossible to achieve. Hence there was a _pressing need to

develop

non-intrusive

testing

methods for RF circuits

[11],

and thus was bom the Built-in-Self Test

(BiST)

approach.

The most important requirement of such

testing

is minimal intrusion.

Any

probing device used should not alter the performance of the circuit

being

tested. This

requirement is a _{particularly challenging} issue in RF _circuits, since even small

inductances and capacitances can have a significant impact on the circuit. The other

requirements are low _power, real estate and _{processing overheads,} and _reliabilityof the

testing

circuitry itself.

Severalattemptshave been madeinrecent literaturetoaddress the problem ofRF

front-end reliability with the view of _quantifying the effect of the various above

mentionedfactors on circuit performancethrough _self-test,

thereby

_attemptingtoimprove

the robustness ofthe RF part shipped to the end customer.

Many

approaches such as the

loop

back technique proposed in

[12]

and the end-to-end approach proposed in

[13]

involve significant _processingand real estate overheads since

they

require thepresence of

additional DSP _processing to achieve self test. Approaches such as the signature test

method proposed in

[14]

are_{very computationally}

intensive,

_requiring a large amount of

off line computation to estimate circuit performance. Current commercial approaches

test costin addition to_{very large}test times to test RFparts.

Power-supply

current based

testing [15,

16]

has been one ofthemore _{promising techniques,} where the_supplycurrent

is _analyzed, and signature patterns _quantify the performance degradation. None of the

above approaches have ledtoa

fully

integrated

testing

solutionfor RFcircuits,as yet.

1.4

Necessity

forthis work

Having

laid-out the background in the previous _sections, we now discuss certain

outstanding

issues,

critical to RFIC performance, which current approaches fail to

address. Thiswork,as willbe _shown,accountsfortheseproblems successfully.

While the chip-package co-design _methodology and BiST approaches address

many issues

by

accounting for parasitics

during

thedesign process

[17],

development of

early design techniques, etc.,

they

failtoaccountforthe

following

problems:

Widetoleranceranges of package parasitics: In currentapproaches,accounting

forpackage parasitics

during

thedesign process does not alleviate theproblem of

tolerances. Since these parasitics are subject to wide variations that cannot be

predicted

during

the design cycle

[18],

the performance of the _{circuitry may}

degrade to sub-optimal levelsonce fabricated and packaged. More

importantly,

it

leads to _{unpredictability} of RFIC performance since these tolerances cannot be

accountedfor

during

simulation,and raises serious_{reliability issues.}

Dependence ofESD protection on environmental conditions: ESD parasitics

can possesslarge tolerances,andthis leadsto the same problem mentioned above.

the RFIC's expected _application, and _any change in ESD devices necessitates a

completere-design ofthe circuitry.

Availability

of different _packaging techniques: In _any of the current

approaches, a change in package alters the parasitic impedances and package

thermal characteristics;this necessitates modificationofthe _existing

design,

or,in

the worst-case, repetition of the entire circuit design cycle. In either _case, it

requires a new fabricationcycle, escalatingcosts.

Correction offaults: It has been already mentioned that no complete integrated

testing

solution exists for RFICs yet.

Testing, however,

_merely quantifies the

performance ofthe circuit, anddoes nothing to increasereliability. Ithas valuein

identifying

chips that degrade beyond acceptable

levels,

and ensures that the

defective product does not reach the end-user. In addition to process

faults,

other

factors such as _switching noise coupled from the digital _module, power _supply

coupling, etc. can degrade performance drastically. Quite _evidently, a circuit

topology

that not just quantifies its performance, but also corrects itself in real

timewill bea

highly

desirablequality;itcan _{significantly improve}reliability.

Hence,

a circuit

topology

that

dynamically

self-corrects itsperformanceto _changing

packages and/or package parasitics, processfaults and _variations,other soft

faults,

and ESD _events, can

help

cut down design cycle

time,

reduce cost and ensure

optimal performance under _varying conditions. Such an approach is a major _step

towards

immunizing

the circuit performance from package _{characteristics,} and

1.5

Preface

to this work

This work presents the first-ever successful attempt at self-corrective RF

circuits. It presents a unique architecture that enables on the

fly

modification in the

performance of RF circuits, and proves the concept

by

demonstrating

a complete

implementation. This architecture sidesteps the _many obstacles that have prevented the

success of such a system so far.

7.5.7 Package Independence

The proposed architecture takes a significant _step towards _addressing a critical

bottleneck in today's RFIC

technology

-packaging effects. It progresses a _{step further}

than _{merely modeling} and _{characterizing} package effects on the _chip; it is an attempt to

render the _{chip independent} of these _{effects, redefining} the co-design paradigm. It

proposes a chip-level solutiontopackage

issues,

and

drastically

reduces chip-dependence

on accurate _modeling and characterization of packages.

By

_ensuring that a single

front-end design will adapt itself

dynamically

to package parasitic _variations, it cuts down on

designcycle timesappreciably; italsofacilitates seamless package portability.

7.5.2 Fault Correction

As mentioned earlier, a low cost solution for RF self _test, with a view towards

improving

reliability ofthe integratedcircuit parthas not yet been observed in published

literature. We propose atechnique to

drastically

increase RF integrated circuit _reliability

not _only

by

_quantifying the performance ofthe RFcircuit _{on-chip but}

by

also _correcting

theinputmatch of an LNA: it is the _{first step}towards thegrand vision of self-corrective

circuits.

Theend-resultisa_methodologythat will _quantify and correctthe performance of

the RFcircuit to accountfor processvariations and faults as well as package and passive

parasitic tolerances. This will not _only make the RF circuit insensitive to package

parasitics but will also allow it to be portable between various packages while

dynamically

adjustingtheperformanceto accountfortheparasiticsin thenew package.

1.53 Organization

A system for the self-correction of the input match for any RF front-end circuit

such as a Low Noise Amplifier

(LNA)

or mixeris described in Chapter 2. A novel

two-tonal approach is presented wherein the

testing

process _{depends solely} on the difference

between two signals that pass through the same _{sensing circuitry, thus rendering} the

entire technique insensitive _{to process, temperature,} power _supply and the precision of

the testsignal itself.

We demonstrate the application ofthis _methodology to correct for shift in input

match

frequency

due to variations in parasitic inductances at the input ofthe LNA and

process faults such as variations in gate-source capacitances. Thechoice ofthis particular

circuit isdeliberate: theLNA is the mostcritical circuit in any RF front end,becausethe

noise and the gain ofthis block most influences the noise figure of the entire front end.

Therefore,

the

testability

and _reliability of this sub-circuit is of prime

importance,

to

ensure _reliability oftheentire RFproduct. The circuitimplementation of all components

proposed technique _{is in itself very} robust and will not be affected

by

variations in

process or temperature. In addition to this, the method also involves low computational

and poweroverheads sinceit does not require the presence of aDSPcore. Thetechnique

uses input signals of moderate precision to test and correct the front-end circuit with

correctiontimes lowerthan30 microseconds. Chapter5 lists the _summary and directions

for futurework.

This work is thefirst_step towards the ultimategoal_ofpackage independent,fault

Chapter

2. ARCHITECTURE

2.1

Why

feedbackwill notwork

2.2The 'Lockedloop' concept

2.3

Sensing

the Inputmatch

2.4 Thenovel

'two-tonal'

approach

2.4 Signal processing 2.6The 'Tapped coil'

2.7 Self-correction algorithm

2.8 Merits ofthisarchitecture

2.1 Why

feedback will notwork

Traditionally,

self-correction in _analog circuits has been achieved

by

_using

voltage or current

feedback,

where a part ofthe output voltage or currentis sampled and

fed back to the input to achieve increased robustness with respect to process variations.

However,

this techniquehas several pitfalls when appliedto theRFdomain. In integrated

RFfront_ends, it is notalways possible to have accessto the output port ofthe individual

circuitto sample the output signal without

influencing

the performance ofthe circuit. As

mentioned in the previous chapter, the entire scheme must be minimally intrusive. In

addition to this, feedback components such as transformers, multipliers, etc., have wide

tolerances _making the entire feedback system unreliable. This approach creates

significantly complex _{stability issues.} In comparison to low

frequency

circuits, RF

circuits are

highly

sensitive to layout parasitics and mutual _coupling effects. Metal trace

parasitics, in theorderof a tenthofa _nano-henry and tens offemto-faradsare no longer

negligible due to operations in theGHz _{domain. While stability is}

inherently

difficultto

complicates the

issue,

degrading

_{both reliability} and predictability. RF circuits with no

feedback are

finely

_balanced.

Introducing

feedback will _essentially re-define the entire

design _paradigm, and destroys our objective of _rendering current RF circuits

fault-tolerant with minimal intrusion. It is thus seen that traditional feedback techniques

introduce significantdesign_{complexity,creating} a needforthe redesignofthe RFcircuit

inquestion as a completefeedback system,withall itsassociated complexity.

Sense Amplifier Peak Detector

Startwith nominal rlesipn Sensecurrent with_minimally intrusive element Amplifysensed current Down-convert signalto baseband

Mapsignalto performance

metric

RF CIRCUIT

Dynamicallymodify designparametersin

RFcircuit

Generate

baseband/digital

signaltomodify

designparameters

Baseband Signal

[image:25.525.20.512.238.507.2]

Processing

Figure 2.1 The self-correction methodology.

2.2

The

'Lockedloop'

concept

Thecurrent work proposes an alternative technique that sensestheperformance of

the feedback circuitry. It is analogous to the locking1 achieved in Phase Locked Loops

(P.L.L.),

and hence the

terminology

'locked loop'. The technique consists of an RF

forward path where RF information (in the case of_{this work, the transient} H.F. current)

correspondingto the circuit performance is sensed with minimal intrusion and amplified

to requiredlevels. As willbe described in greaterdetail in subsequent sections,since this

methodology does not pose _anynoise_{requirements,}simple amplifiers with resistiveloads

can be used to achieve this gain. Also due to the robustness ofthe two-tonal technique,

(described in Section

2.4)

the actual numerical value ofthe gain does not influence the

self-calibration. This amplified information is then down converted to base-band or DC

for further processing. The resultant baseband/digital signal quantifies the performance

metric under question and can be used as a BiST readout. This signal is then used to

modify the requisite design parameters in the RF circuit to correct for the variation in

performance without _{requiring any} redesign of the original circuit. This idea is

summarizedin Figure 2.1.

Since the sensed RF information is not _necessarily at the output _node, the

proposed method lays much greater emphasis on _{avoiding intrusion into} the circuit

performance. In addition tothis, the entire feedback path functions in the low

frequency

or DC domain

thereby

alleviating the stringent noise and aforementioned design

complexity requirements that plague traditional high

frequency

feedback schemes. As

will also be seen, this methodology differs from the traditional feedback concept in one

1

As in P.L.L.'s, the algorithm used in thisworkiteratesthrough a series of_{possibilities,} and attheend of

each cycle computes if it has moved closer to the desired performance. Once a 'lock'

is achieved, the

more principal aspect: the output is neither _sampled, nor fed-back to the input.

Instead,

the performance metric is measured,and a decision is _made,

dynamically,

to _{modify (if}

required) adesign parameterinthecircuit. This

'self-correction'

signalis inthe formof a

digital word, _eliminating the potential problems of noise and precision. Both the input

and output ports ofthe circuit under consideration remain untouched. Since most ofthe

processing circuitry acts on low

frequency

_signals, these circuits will also present

relatively low overheads in the RF front-end. The

following

chapters of this work will

describe the application of this _methodology towards the self-correction of the

input-match of aLNA.

The objective of input match self-correction was addressed

by

a four fold

approach:

firstly,

to sense a signal which is indicative ofthe input match ofthe circuit;

secondly, to process this signal _{appropriately into} a formwhich _{quantitatively describes}

the inputmatch ofthe _{circuit; thirdly,}to use thisinformationto send a signalback to the

circuit where the match can be re-calibrated towards the desired value, and

finally

to

providefor a mechanism in thecircuit which can_adaptivelychange

Sn

inreal timebased

ontheaforementionedfeedbacksignal.

2.3 Sensing

the

Input Match

The _{first step in} this processis to establish a means of_sensing some signal from

the circuit that, with further processing if required, will _ultimately provide information

aboutits input match. RF circuits draw current from the power _supply, which provides

attributes. Some potential placements ofthe_sensing elementfor a single-ended Cascode

LNA areshownin Figure 2.2 [19]:

Placing

it in series with the drain inductor(Figure 2.2

(a))

degrades gain,

S22

and

noisefigure.

It can be placed in series with the bypass capacitor (Figure

2.2(b)),

which is

necessarilypresentinalmost_{every RF}circuit2. Thisplacement

however,

degrades

gain and

S22

significantly.

Placing

it in series with the sourceinductor (Figure

2.2(c)),

and _re-designingthe

input match _along with the _sensingresistor results in minimal impact on

Sn

and

noisefigure.

f _{rtWA_||}

/wy>

|

(a)

(b)

(c)

Fig

2.2 Potentialplacementsfor the_sensing resistor

2

RFcircuitshave bypasscapacitorstoprovidetheH.F.current,sincethepower_supplypathfromthe

[image:28.525.119.383.328.547.2]

Further,

it is advantageous for this element to be a _resistor, as opposed to an

inductor or capacitor . From the above discussion it is evident that, in terms of minimal

intrusion,

placing a small resistorin series with the source inductorresults in the optimal

solution.

This approach creates a voltage indicative of the input match

frequency

with

minimal intrusion on the circuit's behavior. It is possible to distinguish changes in the

current due to faults onthe output side ofthecircuit

by

_usinga similar mechanism at the

input side ofthe next circuit in theRFfront-end chain (for example, the LNAis followed

by

a Mixer).

By

_co-designing the circuit with the _{sensing resistor,} its impact on input

match canbe renderednegligible, and on noise figure and dynamicrange, minimal4.

The current variations in the LNA due to a shift in the input match are of small

magnitude (tens of uA).

Further,

since the resistor value is quite small (7 ohms, in this

work), this voltage needs to _{be sufficiently} amplified before further processing. The

voltagefromthe resistoris fedtoa source follower_stage, which provides isolation to the

LNA fromtherestofthe _sensingcircuitry.

2.4 The

novelTwo-tonal'approach

As will be described later in this chapter, it is the peak-to-peak amplitude of the

voltage across the _sensing resistor that contains input match information and hence we

need toconvert this RF voltage into

DC,

which quantifies Sn. The sensed RFvoltage is

3

The quantification of_anyperformancemetricin aRFcircuit_{generally involvessensing}certain signals at

multiple frequencies. The frequency dependent characteristics of capacitors & inductors complicate this

peak-detected and used for furtherprocessing.The circuitry that performs this operation

iscalledthe 'sensor_chain', andisexplainedin Section 2.5.

One ofthe most importantrequirements ofthis process is to ensure that the

self-correction _{circuitry itself is extremely robust;} process variations and faults in the

self-correction _circuitry should not be mistaken for that of the circuit under consideration.

Towards this _objective, a novel 'two-tonal' approach is presented, which, due to the fact

that its output is the difference of two signals that pass through the same overhead

circuitry, is extremely resilient. Thisapproachfurtheraltogether removes the

dependency

on absolute parameters like accuracyof_gain,

linearity,

etc.

Change in_{VTOnei and}VTOne2correspondingto

leftwardshift of_Sn from 1to3

Tone 1 Tone 2

[image:30.525.41.475.320.639.2]

(a)

(b)

For a given input match, the spectral output of this sensor chain is a _steadily

decreasing

monotonic (almost

linear)

curve as

frequency

increases.

Further,

thecurrent in

the LNA and hence the sensed voltage varies _{monotonically} as the

SM

match is varied.

Toascertaintheexact offsetthroughwhichtheinput

tuning

frequency

needs tobe shifted

and to render this technique independent of process, temperature and power _supply

variations in the _{sensing circuitry}

itself,

we use the two-tonal approach. The success of

this _methodology

depends,

_{among many} other _things, on the careful selection oftones.

They

mustlieon either side ofthe desired input match

frequency

(shown in Figure 2.3 as

Tone 1 and Tone

2)

such that the

Sn

variation lies within their bounds. For example,

suppose theLNA is designed fora nominal match at3 GHzand theexpected inputmatch

variation is between 2.8 GHz and 3.2 GHz. Tone 1 mustbe chosen such that it is less

than 2.8 GHz andtone

2,

greaterthan 3.2 GHz. This selection procedure ensures that the

monotonocityofthe sensed voltage versus input match isconsistent across the

frequency

spread (2.8 GHzto 3.2

GHz,

inthiscase).

Two test signals _{corresponding} to the above frequencies are applied to the LNA

one after the other. Each signal passes through the same _{sensing circuitry} and these

outputs

(Vtonei

and

Vtone2)

are peak detectedand stored ontwo capacitors.

Decreasing

the

input matched

frequency

increases the amplitude ofthe first tone

(Vlonei,

as depicted in

Figure 2.3

(b))

and decreases the amplitude of the second signal

(V,one2,

as depicted in

Figure 2.3 (b)). The difference between

V,onei

and

Vtone2

provides a measure oftheshift in

Si

i, andhencethe

frequency

offset

by

whichinput matchneeds to bemoved tocorrect it

Thefact that bothtones passthrough the same sensor and peak

detector,

and it is

their difference that is _processed, renders this processrobust.

Any

unexpected variation,

for_{example, high ambient}

temperature,

will affectboth _{the tonal-signals equally,} and the

subtracted signal will retainits faithfulness. It is shown in Chapter 4 that this method is

insensitive toprocess _{variations, temperature} and power _supply variations.

Furthermore,

this differential method of _{ascertaining input match}

frequency

_{renders the technique}

immune,

for_example, eventoa 50% variation inthegain ofthe _sensor, tolerances in the

sensingresistor value ortheprecision ofthe inputtestsignal itself. Itmust bementioned

at this point that the use of athird tone at the desired input match

frequency

(3

GHz,

in

the above _example) can also provide quantification ofthe magnitude ofthe input match.

This information can be used to correct the magnitude of the match if it falls below

acceptablelevels.

2.5 Signal Processing

As mentioned in theearlier _sections, the sensed voltage from the LNA is quite

small in magnitude and needs to be amplified. It is then converted to DC

by

peak-detecting

the signal.

Consequently,

_any amplification of the voltage signal mentioned

above need not be noise-freeor low-noise5. This allows one to use_resistors, and simple

single-stage gain configurations (the push-pull amplifier, or the Common Source

amplifier used in this _work) can _amplify the signal _up to a few hundreds of millivolts.

5

We would otherwise be faced with the amusing conundrum of _{requiring LNAs} to _quantify LNA performance.Itshould alsobementionedthat_using othervariantsofRFamplifiers(with_inductors) in the

Robustness canbe accomplished withfeedback inthe amplifier(source

degeneration,

for

example), but after extensive _simulations, it was deemed unnecessary due to the

resilience of the 'two-tonal' approach.

Further,

the amplitude of the test signal can be

considerably higherthan thetypical input signal amplitudes to the

LNA,

withinthe limits

ofits

linearity

and dynamicrange.This in turnbrings downtheamplification needs ofthe

sensing amplifier. This signal isthen input to a peak detectorwhich outputs aDC signal

inproportion to theinputmatch oftheLNA.

The processing circuitryrequired forthiswork consists of:

PMOS Source-follower DC Buffers

RF Sense Amplifier DC Subtractors

RF Peak detector

(PD)

Comparators

Storageelements

(capacitors)

Digital logic and_clocking

The self-correction _algorithm, explained in detail in Section

2.7,

will

elaborate on the

functionality

of each circuit. The output (foreach _tone) from the peak

detector is stored on different capacitors, and the subtraction is performed

by

op-amps.

The op-amps draw theirinputsthrough buffers tominimize chargeloss in thecapacitors

and isolate the peakdetection circuitry. The rest ofthe _{processingcircuitry is}comprised

of_comparators, again derived from op-amps, and _{digital circuitry} and clocking. As will

be seen

later,

a number of

timing

pulses are required for _{this process,} and in this _work,

they

are all derived from a global clock signal. The final output of the _processing

circuitry will be an n-bitdigital word, which willbe fed to theLNA. It will also be seen

technique. It mustonce againbe emphasizedthat none ofthe aforementioned_processing

circuitry hashigh-precision/ accuracyrequirements.

2.6

The 'Tapped

coil'

With the above _setup, the last piece required to complete the 'puzzle' is a

mechanism intheLNA _which, while not_{requiring any}majordesignmodifications, must

allow for dynamic input match changes. The input match ofthe inductively-degenerated

cascodeLNA is given

by

[20]:

Zm=-^

+

j(ay(Ls+Lg)--L-)

C,

GS -GS

Rx

Bias

Rg Lg

a a.

/^ /-yvv^

Out

M2

M1

Ls

[image:34.525.156.393.268.612.2]

Rs S

gm is the transconductance of

M]

(Figure 2.4). It is controlled

by

the size

(W/L)

and the DC current through Mi.

However,

_varying gm to _vary the

input match will also result in other undesirable changes, like power

consumption, gain,dynamic range,etc.

Ls

is thesource coil ofthe LNA. It isresponsible forthe magnitude ofthe

match. In other _{words, if correctly}

balanced,

atthe resonant

frequency,

the

effectiveinput impedancewill be a pure resistive value of:

ry Ofll s r *-C5

Hence varying

Ls

will not_varythe inputmatch frequency.

CGS

isthe gate-source capacitance ofMi.

Adding

additional capacitance in

series with

Lg

will enable us to control

Sn

frequency. In order to be

dynamically

adjustable, a varactor is needed, but unfortunately, MOS

varactors in most RFIC processes

(IBM,

TSMC,

both 0.25 pm and 0.18

pm _processes) musthave one end grounded. Hencethecapacitorhas to be

used in parallel (from gate of

M,

_{to ground),} ratherthan in series.

Using

the capacitor in series has the undesirable effect of_changing the real part

of the input impedance too6, and after numerous simulations it was

concluded that a varactor can be used _{only if} a transformer is used to

couplethe input sourceto theinput port ofthe LNA.

6

This leadstoacompleximpedancenetwork,whichwhentransformedinto itsseriesRLCequivalent(after

Lg

is the gate coil ofthe

LNA,

and _varyingthis element changed _onlythe

Sn

match frequency. In this work,it is thegate coil that acts asthe vehicle

thatcompletestheself-calibration 'locked-loop'.

In orderto_adaptively movethe input match ofthe

LNA,

the gate inductorvalueis

made variable

by

tapping

it at several points. Package parasitics introduce additional

inductance (with very large tolerances) at the input pad ofthe LNA (for example, bond

wires). In this work, we showthatprocessfaults andtheseparasitics canbe accounted for

inreal-time

by

_{re-calibrating}the inputcoil ofthe LNA. Thistechnique alsofacilitatesthe

use ofthe LNA in different packages withdifferent parasitic

inductances;

thecircuit can

re-align itselfto theoriginal inputmatch onthefly.

The gate coil

(Lg)

is designed fora nominal value andthen tapped off atdifferent

intervals in its outer-most _turn, with each

tap

leading

to a switch.

By

including

the

interconnects and switch capacitance in the design process, thiscoil canbecharacterized

togive accurateinductance values. Basedon which switchisturned on, one and _only one

tap

of the coil will be shorted to the input pad of the LNA (Figure

2.5),

and this

tap

determinesthe inputmatch oftheLNA.

2.7

Self-correctionalgorithm

In this section, we describethe _mappingofthe above_methodology to the specific

purpose of_correcting the input match of a LNA. The circuit architecture is depicted in

' _///

.1. Buffers Subtractors

\TappedGate Inductor

,'ofLNA

\

Tap

Switches "

^ntapS)

^-_

yX^7n-bit word

Input Pad

Digital

Logic and

Clocking

[image:37.525.47.478.56.388.2]

Comparators

Figure 2.5 Circuit Architecture forcorrection ofLNA inputmatch

frequency

Stepl:

Having

chosen the two tones (tonel and _tone2) to be used for the input _signals,

the switch _connecting the first

tap

of

Lg

is closed, and a test signal with a

frequency

of

tonel is applied to the inputoftheLNA.

Step

2: The resultant output ofthe PD is stored in capacitor

C]

through switch Si.

Si

is

nowturnedoff.

Step

3: Repeat step 1 for tone2, and storethe resultant output in capacitor C2. Theswitch

discharge path, their leakage is minimal and can be reduced to negligible values

by

choosingappropriatecapacitances.

Step

4: The second

tap

of

Lg

is now closed

(changing

the value of

Le

and _{hence moving}

the input _match) and the above process is _{repeated, storing} the P.D outputs in different

capacitors

(C3

and C4). At this stage of the _process, we have stored the output of the

sensor chain for two tapsofLg.

Step

5: Switches

S5

through

Ss

areturnedon _{simultaneously,connecting}thecapacitorsto

the buffers. For both tapsof

Lg,

the tonal difference amplitudes are calculated

by

means

oftwosubtractors

(Vti

andVT2).

Step

6: Now

VTi

and

V-n

are compared

individually

with

V[DEal,

where

VIDEAl

is the

voltage difference of the two tones for the desired input match. Although in this work

Videal

isafinite valueforease of

implementation,

itcan beensured that

ViDEAL

is 0V

by

slope-correctingthe gain ofthe sense amplifier with respectto

frequency,

thereby making

thecalibration independentof a fixedreference voltage.

Step

7: If

VT)

is closerto

V1DEAL

than

Vj2,

the first

tap

of

Lg

is connected to the input

pad, and self-calibration process is complete. If

VT2

is closerto

VIDEAL,

then steps 1 to 6

are repeated, this timeforthe second and third taps of

Lg

instead ofthe first and second

taps.

Step

8: The self-calibration will be complete when

VT(j)

will be closer to

ViDEAL

than

VT(i+i)

(this is true sincethe amplitude ofthe sensed voltage is monotonic as the input

match

frequency

is varied). Ifthis conditionneveroccurs, then thelast

tap

of

Lg

ischosen

All the switches needtobe turnedon for specificintervals periodically, and these

pulses are derived from a global 2 MHz clock, using

decoding

circuitry. The algorithm

described above follows the linear-search model. Although not _maximally efficient in

termsofthe time _taken,this_methodology provides adequate recompensein return, in the

formof simpler_circuitryand ease ofimplementation.

2.8 Merits

ofthis architecture

Perhapsthe most importantcriterion of _anytest-and-correct _{circuitry is} to

ensure that _{any faults} and variations of the test _circuitry itself will not

mistakenly

identify

non-existent faults. The two-tonal approach, coupled

with simple _{processing circuitry} that does not use _any feedback or

inductors greatlyminimizesthe_probabilityofthat occurrence.

The 'locked-loop' methodology eliminates all the associated _complexity

of atraditional feedback scheme,while _retainingitsusability.

It requires minimal overhead circuitry.

It requires no DSP cores or processor requirements, which is typical of

many RFtestmethods.

It doesnot require A-Dconversion or _{analog memory}cells,and consumes

little power. The entire _processing circuitry, with the exception of a few

latches,

canbeturned off_completelyoncetheprocess iscomplete.

The entire time taken for the self-calibration depends on the number of

processing time. This compares _very

favorably

to times taken

by

current

commercial test schemes

[8],

wherein the

testing

period itself is in the

order ofhundredsof milliseconds.

The only intrusion in this _{methodology is} the small _sensing resistor (7

ohms in this work). The value of the resistor is

flexible,

and can be

reduced further at the cost of

increasing

thegain of the sense amplifier.

This should not pose majorproblems since_cascadingan extra stage ofthe

amplifieris straightforward andincreases gain significantly.

By dynamically

adaptinga single design tovarious package variations and

facilitating

package _portability, it cuts down on design cycle time, and

reduces the dependence of circuit performance on accurate package

characterization and modeling.

The architecture described above _carefully side-steps _many potential

roadblocks in sensingand _correctingthe performance ofRFcircuits. The simplicity

and ease of

implementation,

which is thesubjectofthenext _chapter, is

testimony

to

Chapter

3.

CIRCUIT

IMPLEMENTATION

3.1 Single-ended1.9 GHz LNAwith

Sensing

resistor

-3.1.1 INA Design

-3.1.2 TappedGate coil 3.2 The Sensorchain

-3.2.1 Source Follower

-3.2.2Amplifier

-3.2.3 Peak Detector 3.3. Low

frequency

_{& Digital processing}

3.4.

Timing

3.5. Limitations

3.6. Implementation

Summary

The previous chapterhas described the general _methodology that can be adapted

to specificRFcircuits.

Typically,

RFfront-end circuitry is interfacedto the outside world

(antenna)

through aLow Noise Amplifier (LNA).

Consequently,

it is theLNA that forms

the physical connection between the package and the integrated _circuit, and package

parasitics have a direct impact on its performance.

Further,

the LNA is the most critical

block of _{any front} end since its noise and gain affects the performance of the entire

system. Thus it becomes an ideal choice for this work

-self-correction can be

demonstrated for both processfaultsand packagetolerances/flexibility.

The Single-ended Cascode LNA is perhaps one the most _widely used LNA

topologies [17]. Although the balanced

(differential)

topology7

offers more _advantages,

the single-ended LNAenjoys _popularityfor its ease of

implementation,

and the fact that

it possesseslesserreal-estateand powerconsumption requirements.

7

The self-correction _{methodology described in preceding} chapterhas been applied

to a 1.9 GHz CMOS Single-ended source degenerated narrow-band cascode LNA. This

chapter

discusses,

in

detail,

the implementation of the LNA and all of the associated

processing circuitry. _{All circuitry has been designed and laid out in the IBM 6 Metal}

layer 0.25 pm RFprocess

(CMOS6RF)

with a2.5 Vpower supply.

3.1

Single-ended

1.9 GHz LNA

with

Sensing

resistor

The first stage of a receiveris

typically

alow noise amplifier

(LNA),

whose main

function is to provide enough gain to overcome the noise of subsequent stages. Aside

from providing this gain, while _adding as little noise as _possible, an LNA should

accommodate large signals without

distortion,

and

frequently

present a specified

impedance,

usually 50ohms, to theinput source.

The RF circuit in question, in this case the

LNA,

needs to be co-designed to

accommodate for two factors. It must accommodate a _{minimally intrusive} sense

mechanism that will allow the extraction of its match

information,

and should also

provide for a mechanism to recalibrate the match if deemednecessary, toobtain optimal

performance.

3.1.1LNA Design

The sensing mechanism in the LNA is provided for

by

a7 ohm resistor

(Rs)

that

has been placed in series with thesource

inductor,

in the return current path ofthe LNA.

As explained in Chapter

2,

this is the point of least intrusion for the _resistor, and the

value is the_{optimal solution for the trade-off}

between reducing the degradation of noise

figure and dynamic range ofthe LNA on one side and _achieving sufficient _sensitivityto

be able to_{adequately detectvariations in the input match. Although}

Sn

is also

degraded,

the LNA can be designed with the resistor in the equation for input match to get back

most ofthe input match. Due to the differential nature ofthe _{methodology described in}

previous _sections, the success ofthe calibration approach isunaffected

by

the tolerances

in theactual value oftheresistance.

LNA Inpul Pad

*. To Source

Follower

Y

NMOSSwitches

[image:43.525.116.406.247.500.2]

RS=7D

Figure 3.1SchematicofCascode LNA withtappedgateinductor

The schematic of the LNA is shown in Figure 3.1. The addition of the _sensing

resistancechangesthe inputmatch equation,adding twoextra terms:

Z,

=

^^

₊

j{co(Ls

+L)

)

Co-design with

Rs

involves

designing

Sn

_usingthis modified equation. Atresonance, the

imaginary

part oftheimpedancecancels out since:

COLGS

aX-cs

resulting in aninputresistance of:

'-'GS

The value of

Ls

required to achieve a 50 ohm match is 0.75 nH. The input

transistor ofthe LNA forms a current mirror with the transistor

(M3)

ofthe biascircuit.

The width ofthe biascircuit transistor is chosen tobe one-tenth ofthe inputtransistor to

minimize power overhead of the bias circuit. The _supply voltage and a reference

resistance

(Rbias)

set the current through the left-hand side of the current mirror in

conjunction with the Vgs of the input transistor. Resistance

R2

must be made large

enough so that its noise contribution can be ignored [20]. Since the input resistance is

50ohms,

R2

ischosen tobe 5 Kohms. An external gate-source capacitance

(CGsx,

Figure

3.1)

with a value of0.6 pF has been

included;

thisresults in a nominal

Lg

value of9 nH.

The outputload

(Ld

and

CL)

valueswere chosen toresonateat 1.9GHz.

1

/=

2k^L~Cl

The DC

blocking

capacitorischosento be 30pF sothat its impedanceat 1.9 GHz

is negligible. A power _{supply bypass} capacitor, as discussed _earlier, of 30 pF was

input-side of the LNA only, no impedance-transformation is needed at the output node ofthe

LNA. It is

directly

_connected, through aDC

blocking

capacitor, to theoutput pad.

3.1.2 Tapped

Gate

Coil

The self-correction ofthe LNA in the present case has been achieved

by

_usinga

digitally

tapped gate inductor at the input of the LNA. The

digitally

tapped inductor as

shown in Figure 3.1 consists ofNMOS switches that are connectedto the gate inductorat

various points in its outermost turn and can be used to

tap

into various sections ofthe

gate inductor.

Therefore,

by

turning

the switches on oroff, the value ofthe gate inductor

canbevaried,

thereby

varyingthe

frequency

of match.

It is of significancethat the inductorand its associated parasitics be characterized

accurately. Thegate inductorwas laidout and simulated_using ASITIC [21

]

todetermine

NMOS Switch

/ input

[image:45.525.123.458.374.610.2]

^

pad

Figure 3.2 Layoutofgate coil.The dimensionsare: radius=220

p.m,width of metal

the parasiticinductances andcapacitances associated with the structure (Figure 3.2). This

structure includes all the metal strips used for various interconnections up to the input

pad. The NMOS switches are chosen to haveaW/Lof

68um/0.25um,

_providingan ideal

balance between on-resistance and device capacitance8. The five

'taps'

of the coil are

connected to the NMOS switches, and are referred in subsequent sections as tapl, tap2,

and so_{on, up}to tap5.

Tap

no. Inductancevalue

Corresponding

Si

i freq.

1 7.4nH 1.7 GHz

2 8.1 nH 1.8 GHz

3 _{(nominal value)} 9nH 1.9 GHz

4 10nH 2.0 GHz

5 11 nH 2.1 GHz

ible3.1 Thetappet coil values and cc_^responding

Sn

frequen

portl

9.09 nH

:mm_

120fF

182ohms

5.01 ohms

AA/V

f_res= 6.42 GHz

9nd

Q = _11.20

port2

96.2fF

247 ohms

gnd

K7 ^7

Figure 3.3Pi-modelforthegate coil when

tap

3 isturned on(nominalvalue)

8

The LNA is then co-designed to account for these parasitics (the Pi-model from

ASLTIC is used for the gate _coil, Figure

3.3)

as well as the parasitic capacitances and

finite on-resistance associated withtheMOS switches. Thetapped gate inductor designed

in this work_{has five taps, providing inductance values between 7.4nH and 1 1} nH (Table

3.1). Thesetaps were chosen suchthat the inputmatch oftheLNAcanbe variedfrom 1.7

GHz to 2.1 GHz in stepsof0.1 GHz. Since all the taps have tobe connected to a single

inputpad,care has beentaken to:

Ensure that the interconnects are placed at least three turn widths _away

from thecoil.

All the taps have been drawn out with perpendicular metal strips that are

widerthan the width ofthe inductortominimize additional inductance.

In addition to the above precautions, the whole structure was simulated in ASFTIC to

accountfor any mutualand additional inductances.

The input to the NMOS switch _{array is} a digital word that dictates which one of

the 5 tapsis to be turned on,

thereby

fixing

the value ofthegate inductanceofthe LNA.

Forexample, iftheparasitic inductance ofthepackage

increases,

the

tap

cantherefore be

shifted, reducing the amount of_on-chip gate

inductance,

thus _restoring the

frequency

of

input match for the LNA. The resolution or range of correction can be improved

by

3.2 The

Sensor

chain

3.2.1

Source

Follower

The voltage across the _sensing resistor

Rs

is then fed to a PM0S source follower

with aresistive load. The sourcefollowerserves to isolatethe LNA _{from any processing}

circuitrythatwill follow and also provides a_{relatively broadband interface} to transfer the

sensed signal acrossthe _sensingresistorto the _processingcircuitry. The size ofthesource

followertransistor is kept small so thatit presents a negligible capacitance at the source

nodeofthe LNA. Thiscapacitance isequivalent to _addingadditionalinterconnect related

parasitics atthesource node ofthe

LNA,

andit does not affect the LNAperformance.Its

outputis AC-coupledto the amplifier stagethrough aDC

blocking

capacitor.

Vdd

ffomfts

~p-

-R,

-Ir

Ri*2i

4[Z

Rb2|

HL

to peak detector

Figure 3.4 Thesourcefollowerand amplifier

3.2.2 Amplifier

The magnitudes of voltage variations across

Rs

_{corresponding} to changes in the

amplitude of the test signal can be considerably higher than typical LNA

inputs,

the

resultant gain requirements ofthe amplifier are _verymoderate. In addition to_{this, due} to

the absenceof_anyrestrictions on noisefigure ofthesensed signal simple common source

amplifiers with resistive loads can be used to achieve the required amplification.

Push-pull amplifiers can provide _{very high gain,} but need extensive bias stabilization for a

stable operation. Two cascaded common source stages have been used to construct the

amplifierbecause it ispossibleto AC-couple the sensed signal fromone stageto_another,

while _{providing independent DC biases} to each stage. The minimum required gain from

this amplifier was eight. Simple resistive bias was found to_{be adequately} stable, since it

depends on the ratio of two resistors9.1 K ohm resistive loads have been used because

they

provide the required _gain, while also _presenting optimal source impedance to the

peak detector that follows. No feedback has been incorporated into the amplifier due to

the inherent robustness ofthe two-tonal approach10. As will be shown in Chapter

4,

as

long

as the amplifier can provide a minimal gain at all _{process, supply} and temperature

corners, variations in the numerical value of the gain will not affect the successful

calibration of the RF circuit. The amplifier and the source follower form the sense

amplifier

(SA,

Figure

2.5,

Figure 3.4). Since more common source amplifiers can be

cascaded asdescribed above

(making

itpossibleto achieve higher_gains), it mayeven be

9

The resistive pair mismatchdata in the IBM PDK lists the percentage mismatchfor various resistance pairs. _Bychoosingappropriate widths forthepolysiliconresistors,mismatch canbe minimizedtolessthan

2-3%.

10

The amplifier was designed with source-degeneration feedback & drain-gate resistor _feedback, and

possible to reduce the value ofthe_sensing resistor

by

a few ohms to take advantage of

theavailable _gain, further _minimizingintrusion ontheLNA.

3.2.3 Peak Detector

A standard half-wave diode

(inverting)

voltage doubler (Figure

3.5)

has been

designed to peakdetect the sense amplifier's output. The diodes are current-biased inthe

linearregion forthe range ofits input signals. Since the P.D output has to be stored on

four different capacitors, the output capacitor is duplicated fourtimes

(C\

-C4) and

they

are connected to node

N]

(Figure

3.5)

through transmissiongates (S1-S4). This eliminates

the need for external _memory capacitors. The transmission gates are driven

by

digital

pulses generated in the digital circuitry. The ratio ofinput and output capacitance values

was chosen tobe 5:3toensure optimum chargetransfer.

^ (SeeFigure

2.5)

rtvitctrt*

S5-S9

Figure 3.5 Half-wave

inverting

diodePeak Detector

This peak detector was robust across process, supply and temperature variations.

The drift in diode characteristics will be canceled out sincethe difference oftwo signals

between on-resistance and capacitive parasitics. For _{this application, the} on-resistance is

not a critical issuesince we can always allocate extratimeforthecapacitorstocharge.

The entire sensor chain is also provided with a robust high

frequency

return path

by

connectinga 30pF capacitorbetweenpower _supplyand ground.

3.3

Low-frequency

&

Digital

processing

The outputs of the peak detector are fed to the two subtractors

(Sbi

and

SB2,

Figure

2.5)

through _unity gain buffers. Due to the presence of the

buffers,

the peak

detectorcapacitors have nodischarge path (to discharge the capacitors when required, a

switch is connected across each capacitor and ground. It is only turnedon at the end of a

correction _cycle)

thereby

_retaining all their charge except leakage. Since the signals

handled

by

the _unity gain buffer and the two subtractors are DC voltages, a standard

folded cascode _op-amp (Figure

3.6)

is adequate for both these functions. The folded

cascode configuration is chosen because of its high output

impedance,

high gain and

inherently

highoutput _{swing for}the given process.

The op-amp is biased using a wide _swing cascode current mirror with an external

bias reference of 1 V.

Accuracy

requirements are

fairly

relaxed since the op-amps are

used in a feedback system at DC levelsonly. The op-ampwas designedto have a gain>

1000,

a power consumption <

lmW,

and was compensated with a 7 pF capacitor. The

subtractors were designed to have a gain of

3,

with the corresponding feedback resistor

these resistors", it isnot subjectto huge variations.Thetwo comparators

Cpi

and

Cp2

are

also obtained

by

_using the folded cascode configuration. The outputs ofthe comparators

are usedtodrive standard digital logic.

IJ^HD

d

m

-&, -T^i tw*

fa

J^-r|

"CST WjWi^ZT^ 7P11

ILilM T T."iw"^,

A 1 1 1 1

<

M

'-HI

<S

; -ITTJI

Figure3.6Folded-cascode op-ampconnected as aunity-gain amplifier with current

<